[PATCH] D22420: Fix check for prescheduling to copies from virtual registers

[Elliot Colp via llvm-commits]

colpell created this revision.
colpell added a reviewer: bogner.
colpell added a subscriber: llvm-commits.
Herald added a subscriber: MatzeB.

Currently, this check on line 2834 is an exact copy of a check on line 2810, which SU should have already passed. Given the context and comment above the check ("Avoid prescheduling *to* copies" vs. "Avoid prescheduling copies"), it seems like the intention was to check PredSU instead.

https://reviews.llvm.org/D22420

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -2831,7 +2831,7 @@
       continue;
     // Avoid prescheduling to copies from virtual registers, which don't behave
     // like other nodes from the perspective of scheduling heuristics.
-    if (SDNode *N = SU.getNode())
+    if (SDNode *N = PredSU->getNode())
       if (N->getOpcode() == ISD::CopyFromReg &&
           TargetRegisterInfo::isVirtualRegister
             (cast<RegisterSDNode>(N->getOperand(1))->getReg()))


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