[PATCH] D22397: MIRParser: Rewrite register info initialization; mostly NFC

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added reviewers: qcolombet, arphaman.
MatzeB added a subscriber: llvm-commits.
MatzeB set the repository for this revision to rL LLVM.
Herald added a subscriber: mcrosier.

This changes MachineRegisterInfo to be initializes after parsing all
instructions. This is in preparation for upcoming commits that allow the
register class specification on the operand or deduce them from the
MCInstrDesc.

This commit removes the unused feature of having nonsequential register
numbers. This was confusing anyway as the vreg numbers would be
different after parsing when you had "holes" in your numbering.

This patch also introduces the concept of an incomplete virtual
register. An incomplete virtual register may be used during .mir parsing
to construct MachineOperands without knowing the exact register class
(or register bank) yet.

NFC except for some error messages.

Repository:
  rL LLVM

https://reviews.llvm.org/D22397

Files:
  include/llvm/CodeGen/MachineRegisterInfo.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRParser/MIParser.h
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MachineFunctionAnalysis.cpp
  lib/CodeGen/MachineRegisterInfo.cpp
  test/CodeGen/MIR/X86/undefined-virtual-register.mir
  test/CodeGen/MIR/X86/unused-virtual-register.mir
  test/CodeGen/MIR/X86/virtual-registers.mir

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