[llvm] r274802 - Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc
Michael Kuperstein via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 14:25:27 PDT 2016
Thanks, looking into it!
On Thu, Jul 14, 2016 at 2:25 PM, Jake VanAdrighem <jvanadrighem at gmail.com>
wrote:
> Okay, progress was made! Just posted
> https://llvm.org/bugs/show_bug.cgi?id=28557.
>
> Jake
>
> On Wed, Jul 13, 2016 at 5:18 PM, Michael Kuperstein <mkuper at google.com>
> wrote:
>
>> Yes, this definitely looks like something's gone wrong.
>> Unfortunately, I don't see how I can debug and fix this without a
>> reproducer - in either source or IR form.
>>
>> On Wed, Jul 13, 2016 at 4:33 PM, Jake VanAdrighem <jvanadrighem at gmail.com
>> > wrote:
>>
>>> Here's a vimdiff of the build with/without this commit. Something seems
>>> to have gone wrong here. Let me know if more is needed to properly identify
>>> the bug. Looks like the xorl is above the place we need it and some garbage
>>> value ends up somewhere in memory. Let me know if I'm not seeing something
>>> correctly here.
>>>
>>> [image: Inline image 1]
>>>
>>> On Wed, Jul 13, 2016 at 10:04 AM, Michael Kuperstein <mkuper at google.com>
>>> wrote:
>>>
>>>> Ok, please let me know when you have a reproducer. Sorry for the
>>>> breakage.
>>>>
>>>> Michael
>>>>
>>>> On Tue, Jul 12, 2016 at 8:51 PM, Jake VanAdrighem <
>>>> jvanadrighem at gmail.com> wrote:
>>>>
>>>>>
>>>>>
>>>>> On Tue, Jul 12, 2016 at 8:44 PM, Michael Kuperstein <mkuper at google.com
>>>>> > wrote:
>>>>>
>>>>>> Thanks, Jake!
>>>>>>
>>>>>> Is this with -O0 or in an optimized build? I've since disabled the
>>>>>> pass for -O0 - it should have never run in the first place, and exposed a
>>>>>> fast regalloc bug.
>>>>>>
>>>>>> Michael
>>>>>>
>>>>> An optimized build, -O2 per TU. No LTO.
>>>>>
>>>>> Jake
>>>>>
>>>>>
>>>>>>
>>>>>> On Jul 12, 2016 20:25, "Jake VanAdrighem" <jvanadrighem at gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> By the way, I've bisected this commit as the cause of a miscompile.
>>>>>>> Unfortunately, I don't have a self-contained reproducer yet but I just
>>>>>>> wanted to get the word out.
>>>>>>>
>>>>>>> Jake
>>>>>>>
>>>>>>> On Thu, Jul 7, 2016 at 3:50 PM, Michael Kuperstein via llvm-commits
>>>>>>> <llvm-commits at lists.llvm.org> wrote:
>>>>>>>
>>>>>>>> Author: mkuper
>>>>>>>> Date: Thu Jul 7 17:50:23 2016
>>>>>>>> New Revision: 274802
>>>>>>>>
>>>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=274802&view=rev
>>>>>>>> Log:
>>>>>>>> Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc
>>>>>>>>
>>>>>>>> xorl + setcc is generally the preferred sequence due to the partial
>>>>>>>> register
>>>>>>>> stall setcc + movzbl suffers from. As a bonus, it also encodes one
>>>>>>>> byte smaller.
>>>>>>>> This fixes PR28146.
>>>>>>>>
>>>>>>>> The original commit tried inserting an 8bit-subreg into a GR32 (not
>>>>>>>> GR32_ABCD)
>>>>>>>> which was not appreciated by fast regalloc on 32-bit.
>>>>>>>>
>>>>>>>>
>>>>>>>> Added:
>>>>>>>> llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp
>>>>>>>> - copied, changed from r274770,
>>>>>>>> llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp
>>>>>>>> Modified:
>>>>>>>> llvm/trunk/lib/Target/X86/CMakeLists.txt
>>>>>>>> llvm/trunk/lib/Target/X86/X86.h
>>>>>>>> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>>>>>>> llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/avx512-cmp.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/bmi.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/cmov.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/cmp.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/ctpop-combine.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/fp128-cast.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/fp128-compare.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/return-ext.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/setcc.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse41.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
>>>>>>>> llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
>>>>>>>> +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -19,6 +19,7 @@ set(sources
>>>>>>>> X86FastISel.cpp
>>>>>>>> X86FixupBWInsts.cpp
>>>>>>>> X86FixupLEAs.cpp
>>>>>>>> + X86FixupSetCC.cpp
>>>>>>>> X86FloatingPoint.cpp
>>>>>>>> X86FrameLowering.cpp
>>>>>>>> X86ISelDAGToDAG.cpp
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86.h
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/lib/Target/X86/X86.h (original)
>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86.h Thu Jul 7 17:50:23 2016
>>>>>>>> @@ -59,6 +59,9 @@ FunctionPass *createX86FixupLEAs();
>>>>>>>> /// recalculations.
>>>>>>>> FunctionPass *createX86OptimizeLEAs();
>>>>>>>>
>>>>>>>> +/// Return a pass that transforms setcc + movzx pairs into xor +
>>>>>>>> setcc.
>>>>>>>> +FunctionPass *createX86FixupSetCC();
>>>>>>>> +
>>>>>>>> /// Return a pass that expands WinAlloca pseudo-instructions.
>>>>>>>> FunctionPass *createX86WinAllocaExpander();
>>>>>>>>
>>>>>>>>
>>>>>>>> Copied: llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp (from r274770,
>>>>>>>> llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp)
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp?p2=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&p1=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&r1=274770&r2=274802&rev=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp (original)
>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -156,7 +156,10 @@ bool X86FixupSetCCPass::runOnMachineFunc
>>>>>>>> ++NumSubstZexts;
>>>>>>>> Changed = true;
>>>>>>>>
>>>>>>>> - auto *RC = MRI->getRegClass(ZExt->getOperand(0).getReg());
>>>>>>>> + // On 32-bit, we need to be careful to force an ABCD
>>>>>>>> register.
>>>>>>>> + const TargetRegisterClass *RC =
>>>>>>>> MF.getSubtarget<X86Subtarget>().is64Bit()
>>>>>>>> + ? &X86::GR32RegClass
>>>>>>>> + :
>>>>>>>> &X86::GR32_ABCDRegClass;
>>>>>>>> unsigned ZeroReg = MRI->createVirtualRegister(RC);
>>>>>>>> unsigned InsertReg = MRI->createVirtualRegister(RC);
>>>>>>>>
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -285,7 +285,6 @@ bool X86PassConfig::addInstSelector() {
>>>>>>>> addPass(createCleanupLocalDynamicTLSPass());
>>>>>>>>
>>>>>>>> addPass(createX86GlobalBaseRegPass());
>>>>>>>> -
>>>>>>>> return false;
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -305,6 +304,8 @@ bool X86PassConfig::addPreISel() {
>>>>>>>> }
>>>>>>>>
>>>>>>>> void X86PassConfig::addPreRegAlloc() {
>>>>>>>> + addPass(createX86FixupSetCC());
>>>>>>>> +
>>>>>>>> if (getOptLevel() != CodeGenOpt::None)
>>>>>>>> addPass(createX86OptimizeLEAs());
>>>>>>>>
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
>>>>>>>> (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll Thu
>>>>>>>> Jul 7 17:50:23 2016
>>>>>>>> @@ -1,4 +1,4 @@
>>>>>>>> -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
>>>>>>>> +; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xorl
>>>>>>>>
>>>>>>>> define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
>>>>>>>> entry:
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
>>>>>>>> (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll Thu
>>>>>>>> Jul 7 17:50:23 2016
>>>>>>>> @@ -10,9 +10,9 @@ entry:
>>>>>>>> ; SOURCE-SCHED: subl
>>>>>>>> ; SOURCE-SCHED: movl
>>>>>>>> ; SOURCE-SCHED: sarl
>>>>>>>> +; SOURCE-SCHED: xorl
>>>>>>>> ; SOURCE-SCHED: cmpl
>>>>>>>> ; SOURCE-SCHED: setg
>>>>>>>> -; SOURCE-SCHED: movzbl
>>>>>>>> ; SOURCE-SCHED: movb
>>>>>>>> ; SOURCE-SCHED: xorl
>>>>>>>> ; SOURCE-SCHED: subl
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
>>>>>>>> (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Thu
>>>>>>>> Jul 7 17:50:23 2016
>>>>>>>> @@ -3384,16 +3384,16 @@ declare i32 @llvm.x86.avx.ptestc.256(<4
>>>>>>>> define i32 @test_mm_testnzc_pd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_testnzc_pd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_testnzc_pd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3403,17 +3403,17 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2
>>>>>>>> define i32 @test_mm256_testnzc_pd(<4 x double> %a0, <4 x double>
>>>>>>>> %a1) nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testnzc_pd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testnzc_pd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0,
>>>>>>>> <4 x double> %a1)
>>>>>>>> @@ -3424,16 +3424,16 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.25
>>>>>>>> define i32 @test_mm_testnzc_ps(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_testnzc_ps:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_testnzc_ps:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3443,17 +3443,17 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4
>>>>>>>> define i32 @test_mm256_testnzc_ps(<8 x float> %a0, <8 x float>
>>>>>>>> %a1) nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testnzc_ps:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testnzc_ps:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0,
>>>>>>>> <8 x float> %a1)
>>>>>>>> @@ -3464,17 +3464,17 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.25
>>>>>>>> define i32 @test_mm256_testnzc_si256(<4 x i64> %a0, <4 x i64> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testnzc_si256:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testnzc_si256:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x
>>>>>>>> i64> %a1)
>>>>>>>> @@ -3485,16 +3485,16 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<
>>>>>>>> define i32 @test_mm_testz_pd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_testz_pd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: sete %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_testz_pd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3504,17 +3504,17 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x
>>>>>>>> define i32 @test_mm256_testz_pd(<4 x double> %a0, <4 x double>
>>>>>>>> %a1) nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testz_pd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: sete %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testz_pd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4
>>>>>>>> x double> %a1)
>>>>>>>> @@ -3525,16 +3525,16 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(
>>>>>>>> define i32 @test_mm_testz_ps(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_testz_ps:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: sete %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_testz_ps:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3544,17 +3544,17 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x
>>>>>>>> define i32 @test_mm256_testz_ps(<8 x float> %a0, <8 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testz_ps:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: sete %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testz_ps:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8
>>>>>>>> x float> %a1)
>>>>>>>> @@ -3565,17 +3565,17 @@ declare i32 @llvm.x86.avx.vtestz.ps.256(
>>>>>>>> define i32 @test_mm256_testz_si256(<4 x i64> %a0, <4 x i64> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm256_testz_si256:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; X32-NEXT: sete %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: vzeroupper
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm256_testz_si256:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: vzeroupper
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x
>>>>>>>> i64> %a1)
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -173,16 +173,16 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_comige_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_comige_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -193,16 +193,16 @@ declare i32 @llvm.x86.sse2.comige.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_comigt_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_comigt_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -213,16 +213,16 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_comile_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_comile_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -233,16 +233,16 @@ declare i32 @llvm.x86.sse2.comile.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_comilt_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_comilt_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1264,16 +1264,16 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2
>>>>>>>> define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_ucomige_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_ucomige_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1284,16 +1284,16 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2
>>>>>>>> define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_ucomigt_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_ucomigt_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1304,16 +1304,16 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2
>>>>>>>> define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_ucomile_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomisd %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_ucomile_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomisd %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1324,16 +1324,16 @@ declare i32 @llvm.x86.sse2.ucomile.sd(<2
>>>>>>>> define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse2_ucomilt_sd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomisd %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse2_ucomilt_sd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomisd %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1791,16 +1791,16 @@ declare i32 @llvm.x86.sse41.ptestc(<2 x
>>>>>>>> define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse41_ptestnzc:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vptest %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse41_ptestnzc:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vptest %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x
>>>>>>>> i64> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1811,16 +1811,16 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2
>>>>>>>> define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse41_ptestz:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vptest %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse41_ptestz:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vptest %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64>
>>>>>>>> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1943,23 +1943,29 @@ define i32 @test_x86_sse42_pcmpestri128_
>>>>>>>> }
>>>>>>>>
>>>>>>>>
>>>>>>>> -define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) {
>>>>>>>> +define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) nounwind {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpestria128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: pushl %ebx
>>>>>>>> ; AVX-NEXT: movl $7, %eax
>>>>>>>> ; AVX-NEXT: movl $7, %edx
>>>>>>>> +; AVX-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX-NEXT: seta %bl
>>>>>>>> +; AVX-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX-NEXT: popl %ebx
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpestria128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: pushl %ebx
>>>>>>>> ; AVX512VL-NEXT: movl $7, %eax
>>>>>>>> ; AVX512VL-NEXT: movl $7, %edx
>>>>>>>> +; AVX512VL-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX512VL-NEXT: seta %bl
>>>>>>>> +; AVX512VL-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX512VL-NEXT: popl %ebx
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32
>>>>>>>> 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1991,23 +1997,29 @@ define i32 @test_x86_sse42_pcmpestric128
>>>>>>>> declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x
>>>>>>>> i8>, i32, i8) nounwind readnone
>>>>>>>>
>>>>>>>>
>>>>>>>> -define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) {
>>>>>>>> +define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) nounwind {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpestrio128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: pushl %ebx
>>>>>>>> ; AVX-NEXT: movl $7, %eax
>>>>>>>> ; AVX-NEXT: movl $7, %edx
>>>>>>>> +; AVX-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX-NEXT: seto %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX-NEXT: seto %bl
>>>>>>>> +; AVX-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX-NEXT: popl %ebx
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpestrio128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: pushl %ebx
>>>>>>>> ; AVX512VL-NEXT: movl $7, %eax
>>>>>>>> ; AVX512VL-NEXT: movl $7, %edx
>>>>>>>> +; AVX512VL-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX512VL-NEXT: seto %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX512VL-NEXT: seto %bl
>>>>>>>> +; AVX512VL-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX512VL-NEXT: popl %ebx
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32
>>>>>>>> 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2015,23 +2027,29 @@ define i32 @test_x86_sse42_pcmpestrio128
>>>>>>>> declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x
>>>>>>>> i8>, i32, i8) nounwind readnone
>>>>>>>>
>>>>>>>>
>>>>>>>> -define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) {
>>>>>>>> +define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) nounwind {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpestris128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: pushl %ebx
>>>>>>>> ; AVX-NEXT: movl $7, %eax
>>>>>>>> ; AVX-NEXT: movl $7, %edx
>>>>>>>> +; AVX-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX-NEXT: sets %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX-NEXT: sets %bl
>>>>>>>> +; AVX-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX-NEXT: popl %ebx
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpestris128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: pushl %ebx
>>>>>>>> ; AVX512VL-NEXT: movl $7, %eax
>>>>>>>> ; AVX512VL-NEXT: movl $7, %edx
>>>>>>>> +; AVX512VL-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX512VL-NEXT: sets %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX512VL-NEXT: sets %bl
>>>>>>>> +; AVX512VL-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX512VL-NEXT: popl %ebx
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32
>>>>>>>> 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2039,23 +2057,29 @@ define i32 @test_x86_sse42_pcmpestris128
>>>>>>>> declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x
>>>>>>>> i8>, i32, i8) nounwind readnone
>>>>>>>>
>>>>>>>>
>>>>>>>> -define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) {
>>>>>>>> +define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a2) nounwind {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpestriz128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: pushl %ebx
>>>>>>>> ; AVX-NEXT: movl $7, %eax
>>>>>>>> ; AVX-NEXT: movl $7, %edx
>>>>>>>> +; AVX-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX-NEXT: sete %bl
>>>>>>>> +; AVX-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX-NEXT: popl %ebx
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpestriz128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: pushl %ebx
>>>>>>>> ; AVX512VL-NEXT: movl $7, %eax
>>>>>>>> ; AVX512VL-NEXT: movl $7, %edx
>>>>>>>> +; AVX512VL-NEXT: xorl %ebx, %ebx
>>>>>>>> ; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0
>>>>>>>> -; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> +; AVX512VL-NEXT: sete %bl
>>>>>>>> +; AVX512VL-NEXT: movl %ebx, %eax
>>>>>>>> +; AVX512VL-NEXT: popl %ebx
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32
>>>>>>>> 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2151,16 +2175,16 @@ define i32 @test_x86_sse42_pcmpistri128_
>>>>>>>> define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpistria128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpistria128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %a0, <16
>>>>>>>> x i8> %a1, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2191,16 +2215,16 @@ declare i32 @llvm.x86.sse42.pcmpistric12
>>>>>>>> define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpistrio128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seto %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpistrio128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seto %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %a0, <16
>>>>>>>> x i8> %a1, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2211,16 +2235,16 @@ declare i32 @llvm.x86.sse42.pcmpistrio12
>>>>>>>> define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpistris128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: sets %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpistris128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: sets %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %a0, <16
>>>>>>>> x i8> %a1, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2231,16 +2255,16 @@ declare i32 @llvm.x86.sse42.pcmpistris12
>>>>>>>> define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse42_pcmpistriz128:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse42_pcmpistriz128:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %a0, <16
>>>>>>>> x i8> %a1, i8 7) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2357,16 +2381,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_comige_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_comige_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2377,16 +2401,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_comigt_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_comigt_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2397,16 +2421,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_comile_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_comile_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2417,16 +2441,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_comilt_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_comilt_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2797,16 +2821,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_ucomige_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_ucomige_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2817,16 +2841,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_ucomigt_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_ucomigt_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2837,16 +2861,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_ucomile_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: setae %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_ucomile_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: setae %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2857,16 +2881,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_sse_ucomilt_ss:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_sse_ucomilt_ss:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3778,17 +3802,17 @@ declare i32 @llvm.x86.avx.ptestc.256(<4
>>>>>>>> define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_ptestnzc_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_ptestnzc_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x
>>>>>>>> i64> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3799,17 +3823,17 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<
>>>>>>>> define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_ptestz_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_ptestz_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vptest %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x
>>>>>>>> i64> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4175,16 +4199,16 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(
>>>>>>>> define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestnzc_pd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestnzc_pd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4195,17 +4219,17 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2
>>>>>>>> define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestnzc_pd_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestnzc_pd_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0,
>>>>>>>> <4 x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4216,16 +4240,16 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.25
>>>>>>>> define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestnzc_ps:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestnzc_ps:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4236,17 +4260,17 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4
>>>>>>>> define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x
>>>>>>>> float> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestnzc_ps_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: seta %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestnzc_ps_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: seta %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0,
>>>>>>>> <8 x float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4257,16 +4281,16 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.25
>>>>>>>> define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestz_pd:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestz_pd:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestpd %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4277,17 +4301,17 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x
>>>>>>>> define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x
>>>>>>>> double> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestz_pd_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestz_pd_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestpd %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4298,16 +4322,16 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(
>>>>>>>> define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestz_ps:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestz_ps:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestps %xmm1, %xmm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -4318,17 +4342,17 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x
>>>>>>>> define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x
>>>>>>>> float> %a1) {
>>>>>>>> ; AVX-LABEL: test_x86_avx_vtestz_ps_256:
>>>>>>>> ; AVX: ## BB#0:
>>>>>>>> +; AVX-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; AVX-NEXT: sete %al
>>>>>>>> -; AVX-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX-NEXT: vzeroupper
>>>>>>>> ; AVX-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; AVX512VL-LABEL: test_x86_avx_vtestz_ps_256:
>>>>>>>> ; AVX512VL: ## BB#0:
>>>>>>>> +; AVX512VL-NEXT: xorl %eax, %eax
>>>>>>>> ; AVX512VL-NEXT: vtestps %ymm1, %ymm0
>>>>>>>> ; AVX512VL-NEXT: sete %al
>>>>>>>> -; AVX512VL-NEXT: movzbl %al, %eax
>>>>>>>> ; AVX512VL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8
>>>>>>>> x float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/avx512-cmp.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cmp.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/avx512-cmp.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/avx512-cmp.ll Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -94,9 +94,9 @@ return:
>>>>>>>> define i32 @test6(i32 %a, i32 %b) {
>>>>>>>> ; ALL-LABEL: test6:
>>>>>>>> ; ALL: ## BB#0:
>>>>>>>> +; ALL-NEXT: xorl %eax, %eax
>>>>>>>> ; ALL-NEXT: cmpl %esi, %edi
>>>>>>>> ; ALL-NEXT: sete %al
>>>>>>>> -; ALL-NEXT: movzbl %al, %eax
>>>>>>>> ; ALL-NEXT: retq
>>>>>>>> %cmp = icmp eq i32 %a, %b
>>>>>>>> %res = zext i1 %cmp to i32
>>>>>>>> @@ -106,9 +106,9 @@ define i32 @test6(i32 %a, i32 %b) {
>>>>>>>> define i32 @test7(double %x, double %y) #2 {
>>>>>>>> ; ALL-LABEL: test7:
>>>>>>>> ; ALL: ## BB#0: ## %entry
>>>>>>>> +; ALL-NEXT: xorl %eax, %eax
>>>>>>>> ; ALL-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; ALL-NEXT: setne %al
>>>>>>>> -; ALL-NEXT: movzbl %al, %eax
>>>>>>>> ; ALL-NEXT: retq
>>>>>>>> entry:
>>>>>>>> %0 = fcmp one double %x, %y
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -7,9 +7,9 @@ define i32 @test_kortestz(i16 %a0, i16 %
>>>>>>>> ; CHECK: ## BB#0:
>>>>>>>> ; CHECK-NEXT: kmovw %esi, %k0
>>>>>>>> ; CHECK-NEXT: kmovw %edi, %k1
>>>>>>>> +; CHECK-NEXT: xorl %eax, %eax
>>>>>>>> ; CHECK-NEXT: kortestw %k0, %k1
>>>>>>>> ; CHECK-NEXT: sete %al
>>>>>>>> -; CHECK-NEXT: movzbl %al, %eax
>>>>>>>> ; CHECK-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1)
>>>>>>>> ret i32 %res
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -571,9 +571,9 @@ define <64 x i8> @test17(i64 %x, i32 %y,
>>>>>>>> ; KNL-NEXT: vpbroadcastd %eax, %zmm1 {%k1} {z}
>>>>>>>> ; KNL-NEXT: vpmovdb %zmm1, %xmm1
>>>>>>>> ; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
>>>>>>>> +; KNL-NEXT: xorl %ecx, %ecx
>>>>>>>> ; KNL-NEXT: cmpl %edx, %esi
>>>>>>>> ; KNL-NEXT: setg %cl
>>>>>>>> -; KNL-NEXT: movzbl %cl, %ecx
>>>>>>>> ; KNL-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0
>>>>>>>> ; KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
>>>>>>>> ; KNL-NEXT: vpsllw $7, %ymm0, %ymm0
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/bmi.ll Thu Jul 7 17:50:23 2016
>>>>>>>> @@ -201,7 +201,6 @@ define i1 @and_cmp_const_power_of_two(i3
>>>>>>>> ; CHECK-NEXT: btl %esi, %edi
>>>>>>>> ; CHECK-NEXT: setae %al
>>>>>>>> ; CHECK-NEXT: retq
>>>>>>>> -;
>>>>>>>> %shl = shl i32 1, %y
>>>>>>>> %and = and i32 %x, %shl
>>>>>>>> %cmp = icmp ne i32 %and, %shl
>>>>>>>> @@ -213,12 +212,11 @@ define i32 @and_cmp_not_one_use(i32 %x)
>>>>>>>> ; CHECK-LABEL: and_cmp_not_one_use:
>>>>>>>> ; CHECK: # BB#0:
>>>>>>>> ; CHECK-NEXT: andl $37, %edi
>>>>>>>> +; CHECK-NEXT: xorl %eax, %eax
>>>>>>>> ; CHECK-NEXT: cmpl $37, %edi
>>>>>>>> ; CHECK-NEXT: sete %al
>>>>>>>> -; CHECK-NEXT: movzbl %al, %eax
>>>>>>>> ; CHECK-NEXT: addl %edi, %eax
>>>>>>>> ; CHECK-NEXT: retq
>>>>>>>> -;
>>>>>>>> %and = and i32 %x, 37
>>>>>>>> %cmp = icmp eq i32 %and, 37
>>>>>>>> %ext = zext i1 %cmp to i32
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/cmov.ll Thu Jul 7 17:50:23 2016
>>>>>>>> @@ -120,8 +120,8 @@ declare i32 @printf(i8* nocapture, ...)
>>>>>>>> define i32 @test5(i32* nocapture %P) nounwind readonly {
>>>>>>>> entry:
>>>>>>>> ; CHECK-LABEL: test5:
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> ; CHECK: setg %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> ; CHECK: orl $-2, %eax
>>>>>>>> ; CHECK: ret
>>>>>>>>
>>>>>>>> @@ -134,8 +134,8 @@ entry:
>>>>>>>> define i32 @test6(i32* nocapture %P) nounwind readonly {
>>>>>>>> entry:
>>>>>>>> ; CHECK-LABEL: test6:
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> ; CHECK: setl %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> ; CHECK: leal 4(%rax,%rax,8), %eax
>>>>>>>> ; CHECK: ret
>>>>>>>> %0 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/cmp.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/cmp.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/cmp.ll Thu Jul 7 17:50:23 2016
>>>>>>>> @@ -49,9 +49,9 @@ define i64 @test3(i64 %x) nounwind {
>>>>>>>> %r = zext i1 %t to i64
>>>>>>>> ret i64 %r
>>>>>>>> ; CHECK-LABEL: test3:
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> ; CHECK: testq %rdi, %rdi
>>>>>>>> ; CHECK: sete %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> ; CHECK: ret
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -60,9 +60,9 @@ define i64 @test4(i64 %x) nounwind {
>>>>>>>> %r = zext i1 %t to i64
>>>>>>>> ret i64 %r
>>>>>>>> ; CHECK-LABEL: test4:
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> ; CHECK: testq %rdi, %rdi
>>>>>>>> ; CHECK: setle %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> ; CHECK: ret
>>>>>>>> }
>>>>>>>>
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -34,7 +34,7 @@ define i64 @cmpxchg_sext(i32* %addr, i32
>>>>>>>> ; CHECK-LABEL: cmpxchg_sext:
>>>>>>>> ; CHECK-DAG: cmpxchgl
>>>>>>>> ; CHECK-NOT: cmpl
>>>>>>>> -; CHECK: sete %al
>>>>>>>> +; CHECK: sete %cl
>>>>>>>> ; CHECK: retq
>>>>>>>> %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst
>>>>>>>> seq_cst
>>>>>>>> %success = extractvalue { i32, i1 } %pair, 1
>>>>>>>> @@ -44,10 +44,10 @@ define i64 @cmpxchg_sext(i32* %addr, i32
>>>>>>>>
>>>>>>>> define i32 @cmpxchg_zext(i32* %addr, i32 %desired, i32 %new) {
>>>>>>>> ; CHECK-LABEL: cmpxchg_zext:
>>>>>>>> +; CHECK: xorl %e[[R:[a-z]]]x
>>>>>>>> ; CHECK: cmpxchgl
>>>>>>>> ; CHECK-NOT: cmp
>>>>>>>> -; CHECK: sete [[BYTE:%[a-z0-9]+]]
>>>>>>>> -; CHECK: movzbl [[BYTE]], %eax
>>>>>>>> +; CHECK: sete %[[R]]l
>>>>>>>> %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst
>>>>>>>> seq_cst
>>>>>>>> %success = extractvalue { i32, i1 } %pair, 1
>>>>>>>> %mask = zext i1 %success to i32
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -44,10 +44,10 @@ define i1 @cmpxchg_arithcmp(i128* %addr,
>>>>>>>>
>>>>>>>> define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
>>>>>>>> ; CHECK-LABEL: cmpxchg_zext:
>>>>>>>> +; CHECK: xorl
>>>>>>>> ; CHECK: cmpxchg16b
>>>>>>>> ; CHECK-NOT: cmpq
>>>>>>>> -; CHECK: sete [[BYTE:%[a-z0-9]+]]
>>>>>>>> -; CHECK: movzbl [[BYTE]], %eax
>>>>>>>> +; CHECK: sete
>>>>>>>> %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst
>>>>>>>> seq_cst
>>>>>>>> %success = extractvalue { i128, i1 } %pair, 1
>>>>>>>> %mask = zext i1 %success to i128
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -6,10 +6,10 @@ declare i64 @llvm.ctpop.i64(i64) nounwin
>>>>>>>> define i32 @test1(i64 %x) nounwind readnone {
>>>>>>>> ; CHECK-LABEL: test1:
>>>>>>>> ; CHECK: # BB#0:
>>>>>>>> -; CHECK-NEXT: leaq -1(%rdi), %rax
>>>>>>>> -; CHECK-NEXT: testq %rax, %rdi
>>>>>>>> +; CHECK-NEXT: leaq -1(%rdi), %rcx
>>>>>>>> +; CHECK-NEXT: xorl %eax, %eax
>>>>>>>> +; CHECK-NEXT: testq %rcx, %rdi
>>>>>>>> ; CHECK-NEXT: setne %al
>>>>>>>> -; CHECK-NEXT: movzbl %al, %eax
>>>>>>>> ; CHECK-NEXT: retq
>>>>>>>> %count = tail call i64 @llvm.ctpop.i64(i64 %x)
>>>>>>>> %cast = trunc i64 %count to i32
>>>>>>>> @@ -22,10 +22,10 @@ define i32 @test1(i64 %x) nounwind readn
>>>>>>>> define i32 @test2(i64 %x) nounwind readnone {
>>>>>>>> ; CHECK-LABEL: test2:
>>>>>>>> ; CHECK: # BB#0:
>>>>>>>> -; CHECK-NEXT: leaq -1(%rdi), %rax
>>>>>>>> -; CHECK-NEXT: testq %rax, %rdi
>>>>>>>> +; CHECK-NEXT: leaq -1(%rdi), %rcx
>>>>>>>> +; CHECK-NEXT: xorl %eax, %eax
>>>>>>>> +; CHECK-NEXT: testq %rcx, %rdi
>>>>>>>> ; CHECK-NEXT: sete %al
>>>>>>>> -; CHECK-NEXT: movzbl %al, %eax
>>>>>>>> ; CHECK-NEXT: retq
>>>>>>>> %count = tail call i64 @llvm.ctpop.i64(i64 %x)
>>>>>>>> %cmp = icmp ult i64 %count, 2
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/fp128-cast.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-cast.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/fp128-cast.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/fp128-cast.ll Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -238,6 +238,7 @@ entry:
>>>>>>>> ; X64-LABEL: TestConst128:
>>>>>>>> ; X64: movaps {{.*}}, %xmm1
>>>>>>>> ; X64-NEXT: callq __gttf2
>>>>>>>> +; X64-NEXT: xorl
>>>>>>>> ; X64-NEXT: test
>>>>>>>> ; X64: retq
>>>>>>>> }
>>>>>>>> @@ -277,9 +278,9 @@ entry:
>>>>>>>> ; X64-NEXT: movq (%rsp),
>>>>>>>> ; X64-NEXT: movq %
>>>>>>>> ; X64-NEXT: shrq $32,
>>>>>>>> -; X64: orl
>>>>>>>> +; X64: xorl %eax, %eax
>>>>>>>> +; X64-NEXT: orl
>>>>>>>> ; X64-NEXT: sete %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64: retq
>>>>>>>> ;
>>>>>>>> ; If TestBits128 fails due to any llvm or clang change,
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/fp128-compare.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-compare.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/fp128-compare.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/fp128-compare.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -8,8 +8,9 @@ entry:
>>>>>>>> ret i32 %conv
>>>>>>>> ; CHECK-LABEL: TestComp128GT:
>>>>>>>> ; CHECK: callq __gttf2
>>>>>>>> -; CHECK: setg %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> +; CHECK: xorl %ecx, %ecx
>>>>>>>> +; CHECK: setg %cl
>>>>>>>> +; CHECK: movl %ecx, %eax
>>>>>>>> ; CHECK: retq
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -20,9 +21,10 @@ entry:
>>>>>>>> ret i32 %conv
>>>>>>>> ; CHECK-LABEL: TestComp128GE:
>>>>>>>> ; CHECK: callq __getf2
>>>>>>>> +; CHECK: xorl %ecx, %ecx
>>>>>>>> ; CHECK: testl %eax, %eax
>>>>>>>> -; CHECK: setns %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> +; CHECK: setns %cl
>>>>>>>> +; CHECK: movl %ecx, %eax
>>>>>>>> ; CHECK: retq
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -48,9 +50,10 @@ entry:
>>>>>>>> ret i32 %conv
>>>>>>>> ; CHECK-LABEL: TestComp128LE:
>>>>>>>> ; CHECK: callq __letf2
>>>>>>>> -; CHECK-NEXT: testl %eax, %eax
>>>>>>>> -; CHECK: setle %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> +; CHECK: xorl %ecx, %ecx
>>>>>>>> +; CHECK: testl %eax, %eax
>>>>>>>> +; CHECK: setle %cl
>>>>>>>> +; CHECK: movl %ecx, %eax
>>>>>>>> ; CHECK: retq
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -61,9 +64,10 @@ entry:
>>>>>>>> ret i32 %conv
>>>>>>>> ; CHECK-LABEL: TestComp128EQ:
>>>>>>>> ; CHECK: callq __eqtf2
>>>>>>>> -; CHECK-NEXT: testl %eax, %eax
>>>>>>>> -; CHECK: sete %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> +; CHECK: xorl %ecx, %ecx
>>>>>>>> +; CHECK: testl %eax, %eax
>>>>>>>> +; CHECK: sete %cl
>>>>>>>> +; CHECK: movl %ecx, %eax
>>>>>>>> ; CHECK: retq
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -74,9 +78,10 @@ entry:
>>>>>>>> ret i32 %conv
>>>>>>>> ; CHECK-LABEL: TestComp128NE:
>>>>>>>> ; CHECK: callq __netf2
>>>>>>>> -; CHECK-NEXT: testl %eax, %eax
>>>>>>>> -; CHECK: setne %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> +; CHECK: xorl %ecx, %ecx
>>>>>>>> +; CHECK: testl %eax, %eax
>>>>>>>> +; CHECK: setne %cl
>>>>>>>> +; CHECK: movl %ecx, %eax
>>>>>>>> ; CHECK: retq
>>>>>>>> }
>>>>>>>>
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -3,26 +3,17 @@
>>>>>>>> target datalayout =
>>>>>>>> "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
>>>>>>>> target triple = "x86_64-apple-darwin10.0.0"
>>>>>>>>
>>>>>>>> +declare i32 @foo();
>>>>>>>> +
>>>>>>>> define i32 @f0(i32* nocapture %x) nounwind readonly ssp {
>>>>>>>> entry:
>>>>>>>> - %tmp1 = load i32, i32* %x ; <i32>
>>>>>>>> [#uses=2]
>>>>>>>> - %tobool = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
>>>>>>>> - br i1 %tobool, label %if.end, label %return
>>>>>>>> -
>>>>>>>> -if.end: ; preds = %entry
>>>>>>>> -
>>>>>>>> -; Check that we lower to the short form of cmpl, which has a fixed
>>>>>>>> %eax
>>>>>>>> -; register.
>>>>>>>> -;
>>>>>>>> + %tmp1 = call i32 @foo()
>>>>>>>> ; CHECK: cmpl $16777216, %eax
>>>>>>>> ; CHECK: # encoding: [0x3d,0x00,0x00,0x00,0x01]
>>>>>>>> %cmp = icmp eq i32 %tmp1, 16777216 ; <i1> [#uses=1]
>>>>>>>>
>>>>>>>> %conv = zext i1 %cmp to i32 ; <i32> [#uses=1]
>>>>>>>> ret i32 %conv
>>>>>>>> -
>>>>>>>> -return: ; preds = %entry
>>>>>>>> - ret i32 0
>>>>>>>> }
>>>>>>>>
>>>>>>>> define i32 @f1() nounwind {
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/return-ext.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/return-ext.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/return-ext.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/return-ext.ll Thu Jul 7 17:50:23
>>>>>>>> 2016
>>>>>>>> @@ -42,9 +42,9 @@ entry:
>>>>>>>>
>>>>>>>> ; Except on Darwin, for legacy reasons.
>>>>>>>> ; DARWIN-LABEL: unsigned_i8:
>>>>>>>> -; DARWIN: cmp
>>>>>>>> +; DARWIN: xorl
>>>>>>>> +; DARWIN-NEXT: cmp
>>>>>>>> ; DARWIN-NEXT: sete
>>>>>>>> -; DARWIN-NEXT: movzbl
>>>>>>>> ; DARWIN-NEXT: ret
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -63,9 +63,9 @@ entry:
>>>>>>>>
>>>>>>>> ; Except on Darwin, for legacy reasons.
>>>>>>>> ; DARWIN-LABEL: signed_i8:
>>>>>>>> -; DARWIN: cmp
>>>>>>>> +; DARWIN: xorl
>>>>>>>> +; DARWIN-NEXT: cmp
>>>>>>>> ; DARWIN-NEXT: sete
>>>>>>>> -; DARWIN-NEXT: movzbl
>>>>>>>> ; DARWIN-NEXT: ret
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -85,7 +85,7 @@ entry:
>>>>>>>> ; CHECK-NEXT: addw
>>>>>>>> ; CHECK-NEXT: ret
>>>>>>>>
>>>>>>>> -; Except on Darwin, for legay reasons.
>>>>>>>> +; Except on Darwin, for legacy reasons.
>>>>>>>> ; DARWIN-LABEL: unsigned_i16:
>>>>>>>> ; DARWIN-BWOFF: movw
>>>>>>>> ; DARWIN-BWON: movzwl
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -6,9 +6,9 @@
>>>>>>>> define i32 @t1() nounwind ssp {
>>>>>>>> entry:
>>>>>>>> ; CHECK-LABEL: t1:
>>>>>>>> -; CHECK: cmpl $0, _t1.global
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> +; CHECK-NEXT: cmpl $0, _t1.global
>>>>>>>> ; CHECK-NEXT: setne %al
>>>>>>>> -; CHECK-NEXT: movzbl %al, %eax
>>>>>>>> ; CHECK-NEXT: ret
>>>>>>>> %0 = load i64, i64* @t1.global, align 8
>>>>>>>> %and = and i64 4294967295, %0
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/setcc.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/setcc.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/setcc.ll Thu Jul 7 17:50:23 2016
>>>>>>>> @@ -7,8 +7,8 @@
>>>>>>>> define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
>>>>>>>> entry:
>>>>>>>> ; CHECK-LABEL: t1:
>>>>>>>> +; CHECK: xorl %eax, %eax
>>>>>>>> ; CHECK: seta %al
>>>>>>>> -; CHECK: movzbl %al, %eax
>>>>>>>> ; CHECK: shll $5, %eax
>>>>>>>> %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
>>>>>>>> %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
>>>>>>>> (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Thu
>>>>>>>> Jul 7 17:50:23 2016
>>>>>>>> @@ -593,16 +593,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x
>>>>>>>> define i32 @test_mm_comige_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comige_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comige_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -612,16 +612,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x
>>>>>>>> define i32 @test_mm_comigt_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comigt_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comigt_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -631,16 +631,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x
>>>>>>>> define i32 @test_mm_comile_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comile_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comile_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -650,16 +650,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x
>>>>>>>> define i32 @test_mm_comilt_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comilt_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comilt_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2094,16 +2094,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4
>>>>>>>> define i32 @test_mm_ucomige_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomige_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomige_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2113,16 +2113,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4
>>>>>>>> define i32 @test_mm_ucomigt_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomigt_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomigt_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2132,16 +2132,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4
>>>>>>>> define i32 @test_mm_ucomile_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomile_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomile_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -2151,16 +2151,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4
>>>>>>>> define i32 @test_mm_ucomilt_ss(<4 x float> %a0, <4 x float> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomilt_ss:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomilt_ss:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1)
>>>>>>>> ret i32 %res
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -77,16 +77,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_comige_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_comige_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -97,16 +97,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_comigt_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comiss %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_comigt_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomiss %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -117,16 +117,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_comile_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_comile_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -137,16 +137,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x
>>>>>>>> define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_comilt_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comiss %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_comilt_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomiss %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -517,16 +517,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_ucomige_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_ucomige_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -537,16 +537,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_ucomigt_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: ucomiss %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_ucomigt_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vucomiss %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -557,16 +557,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_ucomile_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_ucomile_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -577,16 +577,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4
>>>>>>>> define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse_ucomilt_ss:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: ucomiss %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse_ucomilt_ss:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vucomiss %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x
>>>>>>>> float> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
>>>>>>>> (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Thu
>>>>>>>> Jul 7 17:50:23 2016
>>>>>>>> @@ -983,16 +983,16 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2
>>>>>>>> define i32 @test_mm_comige_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comige_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comige_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1002,16 +1002,16 @@ declare i32 @llvm.x86.sse2.comige.sd(<2
>>>>>>>> define i32 @test_mm_comigt_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comigt_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comigt_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1021,16 +1021,16 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2
>>>>>>>> define i32 @test_mm_comile_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comile_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comile_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1040,16 +1040,16 @@ declare i32 @llvm.x86.sse2.comile.sd(<2
>>>>>>>> define i32 @test_mm_comilt_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_comilt_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_comilt_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3538,16 +3538,16 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2
>>>>>>>> define i32 @test_mm_ucomige_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomige_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomisd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomige_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomisd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3557,16 +3557,16 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2
>>>>>>>> define i32 @test_mm_ucomigt_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomigt_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomisd %xmm1, %xmm0
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomigt_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomisd %xmm1, %xmm0
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3576,16 +3576,16 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2
>>>>>>>> define i32 @test_mm_ucomile_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomile_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomisd %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: setae %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomile_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomisd %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: setae %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>> @@ -3595,16 +3595,16 @@ declare i32 @llvm.x86.sse2.ucomile.sd(<2
>>>>>>>> define i32 @test_mm_ucomilt_sd(<2 x double> %a0, <2 x double> %a1)
>>>>>>>> nounwind {
>>>>>>>> ; X32-LABEL: test_mm_ucomilt_sd:
>>>>>>>> ; X32: # BB#0:
>>>>>>>> +; X32-NEXT: xorl %eax, %eax
>>>>>>>> ; X32-NEXT: ucomisd %xmm0, %xmm1
>>>>>>>> ; X32-NEXT: seta %al
>>>>>>>> -; X32-NEXT: movzbl %al, %eax
>>>>>>>> ; X32-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; X64-LABEL: test_mm_ucomilt_sd:
>>>>>>>> ; X64: # BB#0:
>>>>>>>> +; X64-NEXT: xorl %eax, %eax
>>>>>>>> ; X64-NEXT: ucomisd %xmm0, %xmm1
>>>>>>>> ; X64-NEXT: seta %al
>>>>>>>> -; X64-NEXT: movzbl %al, %eax
>>>>>>>> ; X64-NEXT: retq
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1)
>>>>>>>> ret i32 %res
>>>>>>>>
>>>>>>>> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
>>>>>>>> URL:
>>>>>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff
>>>>>>>>
>>>>>>>> ==============================================================================
>>>>>>>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)
>>>>>>>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Thu Jul 7
>>>>>>>> 17:50:23 2016
>>>>>>>> @@ -77,16 +77,16 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse2_comige_sd:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse2_comige_sd:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -97,16 +97,16 @@ declare i32 @llvm.x86.sse2.comige.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse2_comigt_sd:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comisd %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse2_comigt_sd:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomisd %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -117,16 +117,16 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse2_comile_sd:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse2_comile_sd:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -137,16 +137,16 @@ declare i32 @llvm.x86.sse2.comile.sd(<2
>>>>>>>> define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double>
>>>>>>>> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse2_comilt_sd:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: comisd %xmm0, %xmm1
>>>>>>>> ; SSE-NEXT: seta %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse2_comilt_sd:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vcomisd %xmm0, %xmm1
>>>>>>>> ; KNL-NEXT: seta %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1152,16 +1152,16 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2
>>>>>>>> define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x
>>>>>>>> double> %a1) {
>>>>>>>> ; SSE-LABEL: test_x86_sse2_ucomige_sd:
>>>>>>>> ; SSE: ## BB#0:
>>>>>>>> +; SSE-NEXT: xorl %eax, %eax
>>>>>>>> ; SSE-NEXT: ucomisd %xmm1, %xmm0
>>>>>>>> ; SSE-NEXT: setae %al
>>>>>>>> -; SSE-NEXT: movzbl %al, %eax
>>>>>>>> ; SSE-NEXT: retl
>>>>>>>> ;
>>>>>>>> ; KNL-LABEL: test_x86_sse2_ucomige_sd:
>>>>>>>> ; KNL: ## BB#0:
>>>>>>>> +; KNL-NEXT: xorl %eax, %eax
>>>>>>>> ; KNL-NEXT: vucomisd %xmm1, %xmm0
>>>>>>>> ; KNL-NEXT: setae %al
>>>>>>>> -; KNL-NEXT: movzbl %al, %eax
>>>>>>>> ; KNL-NEXT: retl
>>>>>>>> %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2
>>>>>>>> x double> %a1) ; <i32> [#uses=1]
>>>>>>>> ret i32 %res
>>>>>>>> @@ -1172,16 +1172,16 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2
>>>>>>>>
>>>>>>> ...
>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
>
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