[PATCH] D22347: [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions

[Matija Amidžić via llvm-commits]

mamidzic created this revision.
mamidzic added reviewers: sdardis, dsanders, hvarga, zbuljan, zoran.jovanovic.
mamidzic added subscribers: sdardis, dsanders, petarj, llvm-commits.
Herald added a reviewer: vkalintiris.

The patch implements microMIPS32r6 CFC1, CFC2, CTC1 and CTC2 instructions.

https://reviews.llvm.org/D22347

Files:
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  test/MC/Disassembler/Mips/micromips32r6/valid.txt
  test/MC/Mips/micromips32r6/valid.s

Index: test/MC/Mips/micromips32r6/valid.s
===================================================================
--- test/MC/Mips/micromips32r6/valid.s
+++ test/MC/Mips/micromips32r6/valid.s
@@ -47,6 +47,10 @@
   cache 1, 8($5)           # CHECK: cache 1, 8($5)      # encoding: [0x20,0x25,0x60,0x08]
   clo $11, $a1             # CHECK: clo $11, $5         # encoding: [0x01,0x65,0x4b,0x3c]
   clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]
+  cfc1 $1, $2              # CHECK: cfc1 $1, $2         # encoding: [0x54,0x22,0x10,0x3b]
+  cfc2 $3, $4              # CHECK: cfc2 $3, $4         # encoding: [0x00,0x64,0xcd,0x3c]
+  ctc1 $5, $6              # CHECK: ctc1 $5, $6         # encoding: [0x54,0xa6,0x18,0x3b]
+  ctc2 $7, $8              # CHECK: ctc2 $7, $8         # encoding: [0x00,0xe8,0xdd,0x3c]
   div $3, $4, $5           # CHECK: div $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x18]
   divu $3, $4, $5          # CHECK: divu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x98]
   ehb                      # CHECK: ehb                 # encoding: [0x00,0x00,0x18,0x00]
Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -62,6 +62,10 @@
 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5)
 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
+0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
+0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
+0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -75,6 +75,10 @@
 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
+class CFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"cfc1", 0b01000000>;
+class CFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"cfc2", 0b1100110100>;
+class CTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"ctc1", 0b01100000>;
+class CTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"ctc2", 0b1101110100>;
 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
@@ -709,6 +713,15 @@
   Format f = FrmFR;
   string BaseOpcode = opstr;
 }
+class CFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
+                          RegisterOperand SrcRC, SDPatternOperator OpNode = null_frag> {
+  dag InOperandList = (ins SrcRC:$impl);
+  dag OutOperandList = (outs DstRC:$rt);
+  string AsmString = !strconcat(opstr, "\t$rt, $impl");
+  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$impl))];
+  Format f = FrmFR;
+  string BaseOpcode = opstr;
+}
 
 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>;
 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
@@ -814,6 +827,13 @@
 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">;
 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">;
 
+class CFC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
+                       HARDFLOAT;
+class CFC2_MMR6_DESC : CFC2_MMR6_DESC_BASE<"cfc2", GPR32Opnd, COP2Opnd>;
+class CTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
+                       HARDFLOAT;
+class CTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"ctc2", COP2Opnd, GPR32Opnd>;
+
 /// Floating Point Instructions
 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
                             InstrItinClass Itin, bit isComm,
@@ -1357,6 +1377,10 @@
                    ISA_MICROMIPS32R6;
 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
+def CFC1_MMR6 : StdMMR6Rel, CFC1_MMR6_DESC, CFC1_MMR6_ENC, ISA_MICROMIPS32R6;
+def CFC2_MMR6 : StdMMR6Rel, CFC2_MMR6_ENC, CFC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def CTC1_MMR6 : StdMMR6Rel, CTC1_MMR6_DESC, CTC1_MMR6_ENC, ISA_MICROMIPS32R6;
+def CTC2_MMR6 : StdMMR6Rel, CTC2_MMR6_ENC, CTC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;


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