[llvm] r275086 - [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities
Zhan Jun Liau via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 11 11:45:04 PDT 2016
Author: zhanjunl
Date: Mon Jul 11 13:45:03 2016
New Revision: 275086
URL: http://llvm.org/viewvc/llvm-project?rev=275086&view=rev
Log:
[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities
Summary: Add support for the z13 instructions LOCHI and LOCGHI which
conditionally load immediate values. Add target instruction info hooks so
that if conversion will allow predication of LHI/LGHI.
Author: RolandF
Reviewers: uweigand
Subscribers: zhanjunl
Commiting on behalf of Roland.
Differential Revision: http://reviews.llvm.org/D22117
Added:
llvm/trunk/test/CodeGen/SystemZ/cond-li.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
llvm/trunk/test/MC/Disassembler/SystemZ/insns-z13.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z13.s
llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s
llvm/trunk/test/MC/SystemZ/insn-good-z13.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Mon Jul 11 13:45:03 2016
@@ -1308,6 +1308,15 @@ class CondUnaryRRF<string mnemonic, bits
let R4 = 0;
}
+class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+ Immediate imm>
+ : InstRIEd<opcode, (outs cls:$R1),
+ (ins imm:$I2, cond4:$valid, cond4:$R3),
+ mnemonic#"$R3\t$R1, $I2", []>,
+ Requires<[FeatureLoadStoreOnCond2]> {
+ let CCMaskLast = 1;
+}
+
// Like CondUnaryRRF, but used for the raw assembly form. The condition-code
// mask is the third operand rather than being part of the mnemonic.
class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
@@ -1320,6 +1329,16 @@ class AsmCondUnaryRRF<string mnemonic, b
let R4 = 0;
}
+class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+ Immediate imm>
+ : InstRIEd<opcode, (outs cls:$R1),
+ (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
+ mnemonic#"\t$R1, $I2, $R3", []>,
+ Requires<[FeatureLoadStoreOnCond2]> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
// Like CondUnaryRRF, but with a fixed CC mask.
class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2, bits<4> ccmask>
@@ -1332,6 +1351,17 @@ class FixedCondUnaryRRF<string mnemonic,
let R4 = 0;
}
+class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+ Immediate imm, bits<4> ccmask>
+ : InstRIEd<opcode, (outs cls:$R1),
+ (ins cls:$R1src, imm:$I2),
+ mnemonic#"\t$R1, $I2", []>,
+ Requires<[FeatureLoadStoreOnCond2]> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+ let R3 = ccmask;
+}
+
class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
RegisterOperand cls, Immediate imm>
: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Mon Jul 11 13:45:03 2016
@@ -530,10 +530,20 @@ static unsigned getConditionalMove(unsig
}
}
+static unsigned getConditionalLoadImmediate(unsigned Opcode) {
+ switch (Opcode) {
+ case SystemZ::LHI: return SystemZ::LOCHI;
+ case SystemZ::LGHI: return SystemZ::LOCGHI;
+ default: return 0;
+ }
+}
+
bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
return true;
+ if (STI.hasLoadStoreOnCond2() && getConditionalLoadImmediate(Opcode))
+ return true;
if (Opcode == SystemZ::Return ||
Opcode == SystemZ::Trap ||
Opcode == SystemZ::CallJG ||
@@ -590,6 +600,16 @@ bool SystemZInstrInfo::PredicateInstruct
MI.setDesc(get(CondOpcode));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(CCValid)
+ .addImm(CCMask)
+ .addReg(SystemZ::CC, RegState::Implicit);
+ return true;
+ }
+ }
+ if (STI.hasLoadStoreOnCond2()) {
+ if (unsigned CondOpcode = getConditionalLoadImmediate(Opcode)) {
+ MI.setDesc(get(CondOpcode));
+ MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+ .addImm(CCValid)
.addImm(CCMask)
.addReg(SystemZ::CC, RegState::Implicit);
return true;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Mon Jul 11 13:45:03 2016
@@ -205,6 +205,10 @@ multiclass CondExtendedMnemonicA<bits<4>
}
def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
+ def LOCHI : FixedCondUnaryRIE<"lochi"##name, 0xEC42, GR64, imm32sx16,
+ ccmask>;
+ def LOCGHI: FixedCondUnaryRIE<"locghi"##name, 0xEC46, GR64, imm64sx16,
+ ccmask>;
def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
@@ -450,6 +454,14 @@ let Uses = [CC] in {
def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
}
+let isCodeGenOnly = 1, Uses = [CC] in {
+ def LOCHI : CondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>;
+ def LOCGHI : CondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>;
+}
+let Uses = [CC] in {
+ def AsmLOCHI : AsmCondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>;
+ def AsmLOCGHI : AsmCondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>;
+}
// Immediate moves.
let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
Modified: llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td Mon Jul 11 13:45:03 2016
@@ -29,6 +29,11 @@ def FeatureLoadStoreOnCond : SystemZFeat
"Assume that the load/store-on-condition facility is installed"
>;
+def FeatureLoadStoreOnCond2 : SystemZFeature<
+ "load-store-on-cond-2", "LoadStoreOnCond2",
+ "Assume that the load/store-on-condition facility 2 is installed"
+>;
+
def FeatureHighWord : SystemZFeature<
"high-word", "HighWord",
"Assume that the high-word facility is installed"
@@ -94,4 +99,4 @@ def : Processor<"z13", NoItineraries,
FeatureFastSerialization, FeatureInterlockedAccess1,
FeatureMiscellaneousExtensions,
FeatureTransactionalExecution, FeatureProcessorAssist,
- FeatureVector]>;
+ FeatureVector, FeatureLoadStoreOnCond2]>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Mon Jul 11 13:45:03 2016
@@ -40,7 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const
HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasTransactionalExecution(false), HasProcessorAssist(false),
- HasVector(false), TargetTriple(TT),
+ HasVector(false), HasLoadStoreOnCond2(false), TargetTriple(TT),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(), FrameLowering() {}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Mon Jul 11 13:45:03 2016
@@ -45,6 +45,7 @@ protected:
bool HasTransactionalExecution;
bool HasProcessorAssist;
bool HasVector;
+ bool HasLoadStoreOnCond2;
private:
Triple TargetTriple;
@@ -85,6 +86,9 @@ public:
// Return true if the target has the load/store-on-condition facility.
bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
+ // Return true if the target has the load/store-on-condition facility 2.
+ bool hasLoadStoreOnCond2() const { return HasLoadStoreOnCond2; }
+
// Return true if the target has the high-word facility.
bool hasHighWord() const { return HasHighWord; }
Added: llvm/trunk/test/CodeGen/SystemZ/cond-li.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-li.ll?rev=275086&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-li.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-li.ll Mon Jul 11 13:45:03 2016
@@ -0,0 +1,23 @@
+; Test LOCHI/LOCGHI
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; CHECK-LABEL: bar1:
+; CHECK: lhi [[REG:%r[0-5]]], 42
+; CHECK: chi %r2, 0
+; CHECK: lochie [[REG]], 0
+define signext i32 @bar1(i32 signext %x) {
+ %cmp = icmp ne i32 %x, 0
+ %.x = select i1 %cmp, i32 42, i32 0
+ ret i32 %.x
+}
+
+; CHECK-LABEL: bar2:
+; CHECK: ltgr [[REG:%r[0-5]]], %r2
+; CHECK: lghi %r2, 42
+; CHECK: locghie %r2, 0
+define signext i64 @bar2(i64 signext %x) {
+ %cmp = icmp ne i64 %x, 0
+ %.x = select i1 %cmp, i64 42, i64 0
+ ret i64 %.x
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns-z13.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns-z13.txt?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns-z13.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns-z13.txt Mon Jul 11 13:45:03 2016
@@ -3313,3 +3313,99 @@
#CHECK: wledb %v31, %v31, 7, 15
0xe7 0xff 0x00 0xff 0x3c 0xc5
+
+#CHECK: lochi %r11, 42, 0
+0xec 0xb0 0x00 0x2a 0x00 0x42
+
+#CHECK: lochio %r11, 42
+0xec 0xb1 0x00 0x2a 0x00 0x42
+
+#CHECK: lochih %r11, 42
+0xec 0xb2 0x00 0x2a 0x00 0x42
+
+#CHECK: lochinle %r11, 42
+0xec 0xb3 0x00 0x2a 0x00 0x42
+
+#CHECK: lochil %r11, -1
+0xec 0xb4 0xff 0xff 0x00 0x42
+
+#CHECK: lochinhe %r11, 42
+0xec 0xb5 0x00 0x2a 0x00 0x42
+
+#CHECK: lochilh %r11, -1
+0xec 0xb6 0xff 0xff 0x00 0x42
+
+#CHECK: lochine %r11, 0
+0xec 0xb7 0x00 0x00 0x00 0x42
+
+#CHECK: lochie %r11, 0
+0xec 0xb8 0x00 0x00 0x00 0x42
+
+#CHECK: lochinlh %r11, 42
+0xec 0xb9 0x00 0x2a 0x00 0x42
+
+#CHECK: lochihe %r11, 255
+0xec 0xba 0x00 0xff 0x00 0x42
+
+#CHECK: lochinl %r11, 255
+0xec 0xbb 0x00 0xff 0x00 0x42
+
+#CHECK: lochile %r11, 32767
+0xec 0xbc 0x7f 0xff 0x00 0x42
+
+#CHECK: lochinh %r11, 32767
+0xec 0xbd 0x7f 0xff 0x00 0x42
+
+#CHECK: lochino %r11, 32512
+0xec 0xbe 0x7f 0x00 0x00 0x42
+
+#CHECK: lochi %r11, 32512, 15
+0xec 0xbf 0x7f 0x00 0x00 0x42
+
+#CHECK: locghi %r11, 42, 0
+0xec 0xb0 0x00 0x2a 0x00 0x46
+
+#CHECK: locghio %r11, 42
+0xec 0xb1 0x00 0x2a 0x00 0x46
+
+#CHECK: locghih %r11, 42
+0xec 0xb2 0x00 0x2a 0x00 0x46
+
+#CHECK: locghinle %r11, 42
+0xec 0xb3 0x00 0x2a 0x00 0x46
+
+#CHECK: locghil %r11, -1
+0xec 0xb4 0xff 0xff 0x00 0x46
+
+#CHECK: locghinhe %r11, 42
+0xec 0xb5 0x00 0x2a 0x00 0x46
+
+#CHECK: locghilh %r11, -1
+0xec 0xb6 0xff 0xff 0x00 0x46
+
+#CHECK: locghine %r11, 0
+0xec 0xb7 0x00 0x00 0x00 0x46
+
+#CHECK: locghie %r11, 0
+0xec 0xb8 0x00 0x00 0x00 0x46
+
+#CHECK: locghinlh %r11, 42
+0xec 0xb9 0x00 0x2a 0x00 0x46
+
+#CHECK: locghihe %r11, 255
+0xec 0xba 0x00 0xff 0x00 0x46
+
+#CHECK: locghinl %r11, 255
+0xec 0xbb 0x00 0xff 0x00 0x46
+
+#CHECK: locghile %r11, 32767
+0xec 0xbc 0x7f 0xff 0x00 0x46
+
+#CHECK: locghinh %r11, 32767
+0xec 0xbd 0x7f 0xff 0x00 0x46
+
+#CHECK: locghino %r11, 32512
+0xec 0xbe 0x7f 0x00 0x00 0x46
+
+#CHECK: locghi %r11, 32512, 15
+0xec 0xbf 0x7f 0x00 0x00 0x46
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z13.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z13.s?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z13.s Mon Jul 11 13:45:03 2016
@@ -1199,3 +1199,26 @@
wledb %v0, %v0, 0, 16
wledb %v0, %v0, -1, 0
wledb %v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: lochie %r0, 66000
+#CHECK: error: invalid operand
+#CHECK: lochie %f0, 0
+#CHECK: error: invalid operand
+#CHECK: lochie 0, %r0
+
+ lochie %r0, 66000
+ lochie %f0, 0
+ lochie 0, %r0
+
+#CHECK: error: invalid operand
+#CHECK: locghie %r0, 66000
+#CHECK: error: invalid operand
+#CHECK: locghie %f0, 0
+#CHECK: error: invalid operand
+#CHECK: locghie 0, %r0
+
+ locghie %r0, 66000
+ locghie %f0, 0
+ locghie 0, %r0
+
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s Mon Jul 11 13:45:03 2016
@@ -1576,3 +1576,14 @@
#CHECK: wledb %v0, %v0, 0, 0
wledb %v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: load store on condition 2)?}}
+#CHECK: lochio %r11, 42
+
+ lochio %r11, 42
+
+#CHECK: error: {{(instruction requires: load store on condition 2)?}}
+#CHECK: locghio %r11, 42
+
+ locghio %r11, 42
+
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z13.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z13.s?rev=275086&r1=275085&r2=275086&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z13.s Mon Jul 11 13:45:03 2016
@@ -5089,3 +5089,71 @@
wledb %v0, %v31, 0, 0
wledb %v31, %v0, 0, 0
wledb %v14, %v17, 4, 10
+
+#CHECK: lochi %r11, 42, 0 # encoding: [0xec,0xb0,0x00,0x2a,0x00,0x42]
+#CHECK: lochio %r11, 42 # encoding: [0xec,0xb1,0x00,0x2a,0x00,0x42]
+#CHECK: lochih %r11, 42 # encoding: [0xec,0xb2,0x00,0x2a,0x00,0x42]
+#CHECK: lochinle %r11, 42 # encoding: [0xec,0xb3,0x00,0x2a,0x00,0x42]
+#CHECK: lochil %r11, -1 # encoding: [0xec,0xb4,0xff,0xff,0x00,0x42]
+#CHECK: lochinhe %r11, 42 # encoding: [0xec,0xb5,0x00,0x2a,0x00,0x42]
+#CHECK: lochilh %r11, -1 # encoding: [0xec,0xb6,0xff,0xff,0x00,0x42]
+#CHECK: lochine %r11, 0 # encoding: [0xec,0xb7,0x00,0x00,0x00,0x42]
+#CHECK: lochie %r11, 0 # encoding: [0xec,0xb8,0x00,0x00,0x00,0x42]
+#CHECK: lochinlh %r11, 42 # encoding: [0xec,0xb9,0x00,0x2a,0x00,0x42]
+#CHECK: lochihe %r11, 255 # encoding: [0xec,0xba,0x00,0xff,0x00,0x42]
+#CHECK: lochinl %r11, 255 # encoding: [0xec,0xbb,0x00,0xff,0x00,0x42]
+#CHECK: lochile %r11, 32767 # encoding: [0xec,0xbc,0x7f,0xff,0x00,0x42]
+#CHECK: lochinh %r11, 32767 # encoding: [0xec,0xbd,0x7f,0xff,0x00,0x42]
+#CHECK: lochino %r11, 32512 # encoding: [0xec,0xbe,0x7f,0x00,0x00,0x42]
+#CHECK: lochi %r11, 32512, 15 # encoding: [0xec,0xbf,0x7f,0x00,0x00,0x42]
+
+ lochi %r11, 42, 0
+ lochio %r11, 42
+ lochih %r11, 42
+ lochinle %r11, 42
+ lochil %r11, -1
+ lochinhe %r11, 42
+ lochilh %r11, -1
+ lochine %r11, 0
+ lochie %r11, 0
+ lochinlh %r11, 42
+ lochihe %r11, 255
+ lochinl %r11, 255
+ lochile %r11, 32767
+ lochinh %r11, 32767
+ lochino %r11, 32512
+ lochi %r11, 32512, 15
+
+#CHECK: locghi %r11, 42, 0 # encoding: [0xec,0xb0,0x00,0x2a,0x00,0x46]
+#CHECK: locghio %r11, 42 # encoding: [0xec,0xb1,0x00,0x2a,0x00,0x46]
+#CHECK: locghih %r11, 42 # encoding: [0xec,0xb2,0x00,0x2a,0x00,0x46]
+#CHECK: locghinle %r11, 42 # encoding: [0xec,0xb3,0x00,0x2a,0x00,0x46]
+#CHECK: locghil %r11, -1 # encoding: [0xec,0xb4,0xff,0xff,0x00,0x46]
+#CHECK: locghinhe %r11, 42 # encoding: [0xec,0xb5,0x00,0x2a,0x00,0x46]
+#CHECK: locghilh %r11, -1 # encoding: [0xec,0xb6,0xff,0xff,0x00,0x46]
+#CHECK: locghine %r11, 0 # encoding: [0xec,0xb7,0x00,0x00,0x00,0x46]
+#CHECK: locghie %r11, 0 # encoding: [0xec,0xb8,0x00,0x00,0x00,0x46]
+#CHECK: locghinlh %r11, 42 # encoding: [0xec,0xb9,0x00,0x2a,0x00,0x46]
+#CHECK: locghihe %r11, 255 # encoding: [0xec,0xba,0x00,0xff,0x00,0x46]
+#CHECK: locghinl %r11, 255 # encoding: [0xec,0xbb,0x00,0xff,0x00,0x46]
+#CHECK: locghile %r11, 32767 # encoding: [0xec,0xbc,0x7f,0xff,0x00,0x46]
+#CHECK: locghinh %r11, 32767 # encoding: [0xec,0xbd,0x7f,0xff,0x00,0x46]
+#CHECK: locghino %r11, 32512 # encoding: [0xec,0xbe,0x7f,0x00,0x00,0x46]
+#CHECK: locghi %r11, 32512, 15 # encoding: [0xec,0xbf,0x7f,0x00,0x00,0x46]
+
+ locghi %r11, 42, 0
+ locghio %r11, 42
+ locghih %r11, 42
+ locghinle %r11, 42
+ locghil %r11, -1
+ locghinhe %r11, 42
+ locghilh %r11, -1
+ locghine %r11, 0
+ locghie %r11, 0
+ locghinlh %r11, 42
+ locghihe %r11, 255
+ locghinl %r11, 255
+ locghile %r11, 32767
+ locghinh %r11, 32767
+ locghino %r11, 32512
+ locghi %r11, 32512, 15
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