[llvm] r275050 - [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 11 00:41:57 PDT 2016
Author: zbuljan
Date: Mon Jul 11 02:41:56 2016
New Revision: 275050
URL: http://llvm.org/viewvc/llvm-project?rev=275050&view=rev
Log:
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824
Added:
llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll
llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s
llvm/trunk/test/MC/Mips/mips32r5/invalid.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
llvm/trunk/test/MC/Mips/mips32r6/invalid.s
llvm/trunk/test/MC/Mips/mips64r5/invalid.s
llvm/trunk/test/MC/Mips/mips64r6/invalid.s
llvm/trunk/test/MC/Mips/target-soft-float.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Jul 11 02:41:56 2016
@@ -1063,10 +1063,17 @@ public:
// and determine whether a Value is a constant or not.
template <unsigned Bits, unsigned ShiftAmount = 0>
bool isMemWithSimmOffset() const {
- return isMem() && getMemBase()->isGPRAsmReg() &&
- (isa<MCTargetExpr>(getMemOff()) ||
- (isConstantMemOff() &&
- isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())));
+ if (!isMem())
+ return false;
+ if (!getMemBase()->isGPRAsmReg())
+ return false;
+ if (isa<MCTargetExpr>(getMemOff()) ||
+ (isConstantMemOff() &&
+ isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
+ return true;
+ MCValue Res;
+ bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
+ return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
}
bool isMemWithGRPMM16Base() const {
return isMem() && getMemBase()->isMM16AsmReg();
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon Jul 11 02:41:56 2016
@@ -354,6 +354,10 @@ static DecodeStatus DecodeFMem(MCInst &I
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
@@ -366,6 +370,10 @@ static DecodeStatus DecodeFMemCop2R6(MCI
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1704,6 +1712,24 @@ static DecodeStatus DecodeFMem(MCInst &I
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ // This function is the same as DecodeFMem but with the Reg and Base fields
+ // swapped according to microMIPS spec.
+ int Offset = SignExtend32<16>(Insn & 0xffff);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+
+ Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFMem2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1757,6 +1783,23 @@ static DecodeStatus DecodeFMemCop2R6(MCI
return MCDisassembler::Success;
}
+
+static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ int Offset = SignExtend32<11>(Insn & 0x07ff);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+ Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn,
uint64_t Address,
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Mon Jul 11 02:41:56 2016
@@ -878,6 +878,19 @@ getMemEncodingMMImm9(const MCInst &MI, u
}
unsigned MipsMCCodeEmitter::
+getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
+ assert(MI.getOperand(OpNo).isReg());
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
+ STI) << 16;
+ unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
+
+ return (OffBits & 0x07FF) | RegBits;
+}
+
+unsigned MipsMCCodeEmitter::
getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h Mon Jul 11 02:41:56 2016
@@ -204,6 +204,9 @@ public:
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Mon Jul 11 02:41:56 2016
@@ -1060,3 +1060,35 @@ class POOL32I_BRANCH_COP_1_2_FM_MMR6<str
let Inst{20-16} = rt;
let Inst{15-0} = offset;
}
+
+class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
+ : MMR6Arch<instr_asm> {
+ bits<5> ft;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<16> offset = addr{15-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = funct;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = base;
+ let Inst{15-0} = offset;
+}
+
+class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> rt;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<11> offset = addr{10-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b001000;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = base;
+ let Inst{15-12} = funct;
+ let Inst{11} = 0;
+ let Inst{10-0} = offset;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon Jul 11 02:41:56 2016
@@ -223,6 +223,12 @@ class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_
class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
+class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
+class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
+class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
+class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
+class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
+class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd>
@@ -756,6 +762,58 @@ class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DE
II_MFHC1>, HARDFLOAT, FGR_64;
class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
+class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
+ dag InOperandList = (ins mem_mm_16:$addr);
+ dag OutOperandList = (outs FGR64Opnd:$ft);
+ string AsmString = !strconcat("ldc1", "\t$ft, $addr");
+ list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = II_LDC1;
+ string BaseOpcode = "ldc1";
+ bit mayLoad = 1;
+ let DecoderMethod = "DecodeFMemMMR2";
+}
+
+class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
+ dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
+ dag OutOperandList = (outs);
+ string AsmString = !strconcat("sdc1", "\t$ft, $addr");
+ list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = II_SDC1;
+ string BaseOpcode = "sdc1";
+ bit mayStore = 1;
+ let DecoderMethod = "DecodeFMemMMR2";
+}
+
+class LDC2_LWC2_MMR6_DESC_BASE<string opstr> {
+ dag OutOperandList = (outs COP2Opnd:$rt);
+ dag InOperandList = (ins mem_mm_11:$addr);
+ string AsmString = !strconcat(opstr, "\t$rt, $addr");
+ list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = NoItinerary;
+ string BaseOpcode = opstr;
+ bit mayLoad = 1;
+ string DecoderMethod = "DecodeFMemCop2MMR6";
+}
+class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2">;
+class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2">;
+
+class SDC2_SWC2_MMR6_DESC_BASE<string opstr> {
+ dag OutOperandList = (outs);
+ dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
+ string AsmString = !strconcat(opstr, "\t$rt, $addr");
+ list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
+ Format f = FrmFI;
+ InstrItinClass Itinerary = NoItinerary;
+ string BaseOpcode = opstr;
+ bit mayStore = 1;
+ string DecoderMethod = "DecodeFMemCop2MMR6";
+}
+class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">;
+class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">;
+
/// Floating Point Instructions
class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
InstrItinClass Itin, bit isComm,
@@ -1577,6 +1635,18 @@ def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst
ISA_MICROMIPS32R6;
def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
ISA_MICROMIPS32R6;
+let DecoderNamespace = "MicroMips32r6FP64" in {
+ def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
+ ISA_MICROMIPS32R6 {
+ let BaseOpcode = "LDC164";
+ }
+ def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+}
+def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
}
def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
@@ -1697,3 +1767,8 @@ def : MipsPat<(not GPRMM16:$in),
(NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
def : MipsPat<(not GPR32:$in),
(NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
+// Patterns for load with a reg+imm operand.
+let AddedComplexity = 41 in {
+ def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
+ def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Mon Jul 11 02:41:56 2016
@@ -17,12 +17,6 @@ def FMUL_MM : MMRel, ADDS_FT<"mul.d", A
def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
ADDS_FM_MM<1, 0x70>;
-def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>;
-def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
- LW_FM_MM<0x26>;
-def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
-def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
- LW_FM_MM<0x2e>;
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
@@ -147,4 +141,29 @@ let AdditionalPredicates = [InMicroMips]
MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
+ let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
+ def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
+ LW_FM_MM<0x2f>, FGR_32 {
+ let BaseOpcode = "LDC132";
+ }
+ def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
+ LW_FM_MM<0x2e>, FGR_32;
+ def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
+ LW_FM_MM<0x27>;
+ def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
+ LW_FM_MM<0x26>;
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// Floating Point Patterns
+//===----------------------------------------------------------------------===//
+let AdditionalPredicates = [InMicroMips] in {
+ // Patterns for loads/stores with a reg+imm operand.
+ let AddedComplexity = 40 in {
+ def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
+ def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
+ def : LoadRegImmPat<LWC1_MM, f32, load>;
+ def : StoreRegImmPat<SWC1_MM, f32>;
+ }
}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Mon Jul 11 02:41:56 2016
@@ -1,4 +1,6 @@
-def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
+def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;
+def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;
+def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;
def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
def simm9_addiusp : Operand<i32> {
@@ -106,6 +108,14 @@ def mem_mm_9 : Operand<i32> {
let OperandType = "OPERAND_MEMORY";
}
+def mem_mm_11 : Operand<i32> {
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops GPR32, simm11);
+ let EncoderMethod = "getMemEncodingMMImm11";
+ let ParserMatchClass = MipsMemSimm11AsmOperand;
+ let OperandType = "OPERAND_MEMORY";
+}
+
def mem_mm_12 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm12);
@@ -118,7 +128,7 @@ def mem_mm_16 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncodingMMImm16";
- let ParserMatchClass = MipsMemAsmOperand;
+ let ParserMatchClass = MipsMemSimm16AsmOperand;
let OperandType = "OPERAND_MEMORY";
}
@@ -740,8 +750,8 @@ let DecoderNamespace = "MicroMips", Pred
/// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in {
- def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
- def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
+ def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x7>;
+ def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x5>;
def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
addrDefault>, MMRel, LW_FM_MM<0xf>;
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Mon Jul 11 02:41:56 2016
@@ -793,12 +793,14 @@ let AdditionalPredicates = [NotInMicroMi
def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
-def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
+ def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
}
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
-def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
+}
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
@@ -831,9 +833,6 @@ let AdditionalPredicates = [NotInMicroMi
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
-}
-def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
-let AdditionalPredicates = [NotInMicroMips] in {
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
@@ -846,8 +845,9 @@ let AdditionalPredicates = [NotInMicroMi
HARDFLOAT;
def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
+ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
}
-def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
//===----------------------------------------------------------------------===//
//
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Jul 11 02:41:56 2016
@@ -84,7 +84,19 @@ bool MipsDAGToDAGISel::selectIntAddr(SDV
return false;
}
-bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
+bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ llvm_unreachable("Unimplemented function.");
+ return false;
+}
+
+bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ llvm_unreachable("Unimplemented function.");
+ return false;
+}
+
+bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
llvm_unreachable("Unimplemented function.");
return false;
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h Mon Jul 11 02:41:56 2016
@@ -65,9 +65,15 @@ private:
virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
- virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
+ virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
+ virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
+ virtual bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Jul 11 02:41:56 2016
@@ -160,18 +160,18 @@ class MTC1_64_FT<string opstr, RegisterO
let Constraints = "$fs = $fs_in";
}
-class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
- SDPatternOperator OpNode= null_frag> :
- InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
+ InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
HARDFLOAT {
let DecoderMethod = "DecodeFMem";
let mayLoad = 1;
}
-class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
- SDPatternOperator OpNode= null_frag> :
- InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
+ InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
let DecoderMethod = "DecodeFMem";
let mayStore = 1;
@@ -400,20 +400,30 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opn
}
/// Floating Point Memory Instructions
-def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
-def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
+ LW_FM<0x31>;
+ def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
+ LW_FM<0x39>;
+}
-let DecoderNamespace = "Mips64" in {
- def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
- FGR_64;
- def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
- FGR_64;
+let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in {
+ def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
+ LW_FM<0x35>, ISA_MIPS2, FGR_64 {
+ let BaseOpcode = "LDC164";
+ }
+ def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
+ LW_FM<0x3d>, ISA_MIPS2, FGR_64;
}
-def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
- ISA_MIPS2, FGR_32;
-def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
- ISA_MIPS2, FGR_32;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
+ load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
+ let BaseOpcode = "LDC132";
+ }
+ def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
+ LW_FM<0x3d>, ISA_MIPS2, FGR_32;
+}
// Indexed loads and stores.
// Base register + offset register addressing mode (indicated by "x" in the
@@ -632,13 +642,15 @@ def : MipsPat<(f64 (fextend FGR32Opnd:$s
(CVT_D64_S FGR32Opnd:$src)>, FGR_64;
// Patterns for loads/stores with a reg+imm operand.
-let AddedComplexity = 40 in {
- def : LoadRegImmPat<LWC1, f32, load>;
- def : StoreRegImmPat<SWC1, f32>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ let AddedComplexity = 40 in {
+ def : LoadRegImmPat<LWC1, f32, load>;
+ def : StoreRegImmPat<SWC1, f32>;
- def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
- def : StoreRegImmPat<SDC164, f64>, FGR_64;
+ def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
+ def : StoreRegImmPat<SDC164, f64>, FGR_64;
- def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
- def : StoreRegImmPat<SDC1, f64>, FGR_32;
+ def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
+ def : StoreRegImmPat<SDC1, f64>, FGR_32;
+ }
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Jul 11 02:41:56 2016
@@ -1742,9 +1742,10 @@ let AdditionalPredicates = [NotInMicroMi
/// Load and Store Instructions
/// aligned
-def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
-def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
- LW_FM<0x24>;
+def LB : LoadMemory<"lb", GPR32Opnd, mem_simm16, sextloadi8, II_LB>, MMRel,
+ LW_FM<0x20>;
+def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simm16, zextloadi8, II_LBU,
+ addrDefault>, MMRel, LW_FM<0x24>;
let AdditionalPredicates = [NotInMicroMips] in {
def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
addrDefault>, MMRel, LW_FM<0x21>;
@@ -1775,14 +1776,14 @@ def SWR : StoreLeftRight<"swr", MipsSWR,
let AdditionalPredicates = [NotInMicroMips] in {
// COP2 Memory Instructions
-def LWC2 : LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>,
+def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>,
ISA_MIPS1_NOT_32R6_64R6;
-def SWC2 : SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, LW_FM<0x3a>,
- ISA_MIPS1_NOT_32R6_64R6;
-def LDC2 : LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>,
- ISA_MIPS2_NOT_32R6_64R6;
-def SDC2 : SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, LW_FM<0x3e>,
+def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>,
+ LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6;
+def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>,
ISA_MIPS2_NOT_32R6_64R6;
+def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>,
+ LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6;
// COP3 Memory Instructions
let DecoderNamespace = "COP3_" in {
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Mon Jul 11 02:41:56 2016
@@ -403,6 +403,18 @@ bool MipsSEDAGToDAGISel::selectAddrRegIm
return false;
}
+/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
+bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ if (selectAddrFrameIndex(Addr, Base, Offset))
+ return true;
+
+ if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
+ return true;
+
+ return false;
+}
+
/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
@@ -426,12 +438,24 @@ bool MipsSEDAGToDAGISel::selectAddrRegIm
return false;
}
-bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
+bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ return selectAddrRegImm11(Addr, Base, Offset) ||
+ selectAddrDefault(Addr, Base, Offset);
+}
+
+bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
return selectAddrRegImm12(Addr, Base, Offset) ||
selectAddrDefault(Addr, Base, Offset);
}
+bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ return selectAddrRegImm16(Addr, Base, Offset) ||
+ selectAddrDefault(Addr, Base, Offset);
+}
+
bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h Mon Jul 11 02:41:56 2016
@@ -60,14 +60,23 @@ private:
bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
+ bool selectAddrRegImm11(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
bool selectAddrRegImm16(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
- bool selectIntAddrMM(SDValue Addr, SDValue &Base,
- SDValue &Offset) const override;
+ bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const override;
+
+ bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const override;
+
+ bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const override;
bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
Modified: llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll Mon Jul 11 02:41:56 2016
@@ -18,6 +18,8 @@
; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
+
; Test the the callee-saved registers are callee-saved as specified by section
; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
@@ -109,3 +111,6 @@ entry:
; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp)
; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp)
; N64: addiu $sp, $sp, 64
+
+; Check the mapping between LDC164 and LDC1_64_MMR6.
+; MM32R6: ldc1
Added: llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll?rev=275050&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll Mon Jul 11 02:41:56 2016
@@ -0,0 +1,50 @@
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
+; RUN: -relocation-model=pic < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM32
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
+; RUN: -relocation-model=pic < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM32
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
+; RUN: -relocation-model=pic < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM64
+
+ at gf0 = external global float
+
+define float @test_lwc1() {
+entry:
+; CHECK-LABEL: test_lwc1
+; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
+; MM32: lwc1 $f0, 0($[[R3]])
+
+; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
+; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
+; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
+; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
+; MM64: lwc1 $f0, 0($[[R3]])
+
+ %0 = load float, float* @gf0, align 4
+ ret float %0
+}
+
+define void @test_swc1(float %a) {
+entry:
+; CHECK-LABEL: test_swc1
+; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
+; MM32: swc1 $f12, 0($[[R3]])
+
+; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
+; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
+; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
+; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
+; MM64: swc1 $f12, 0($[[R3]])
+
+ store float %a, float* @gf0, align 4
+ ret void
+}
+
Modified: llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll Mon Jul 11 02:41:56 2016
@@ -2,6 +2,8 @@
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8
@@ -12,10 +14,10 @@ define float @funcfl1() nounwind readonl
entry:
; CHECK-N64: funcfl1
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
+; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfl1
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
+; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load float, float* @f0, align 4
ret float %0
}
@@ -24,11 +26,11 @@ define double @funcfl2() nounwind readon
entry:
; CHECK-N64: funcfl2
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
+; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfl2
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
- %0 = load double, double* @d0, align 8
+; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
+ %0 = load double, double* @d0, align 8
ret double %0
}
@@ -36,12 +38,12 @@ define void @funcfs1() nounwind {
entry:
; CHECK-N64: funcfs1
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
+; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfs1
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
- %0 = load float, float* @f1, align 4
- store float %0, float* @f0, align 4
+; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
+ %0 = load float, float* @f1, align 4
+ store float %0, float* @f0, align 4
ret void
}
@@ -49,12 +51,12 @@ define void @funcfs2() nounwind {
entry:
; CHECK-N64: funcfs2
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
+; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfs2
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
- %0 = load double, double* @d1, align 8
- store double %0, double* @d0, align 8
+; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
+ %0 = load double, double* @d1, align 8
+ store double %0, double* @d0, align 8
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll Mon Jul 11 02:41:56 2016
@@ -5,6 +5,10 @@
; RUN: FileCheck %s -check-prefixes=ALL,32R2-LDXC1
; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1
+; RUN: llc -march=mipsel -mcpu=mips32r3 -mattr=+micromips \
+; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM
; Check that -mno-ldc1-sdc1 disables [sl]dc1
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
@@ -16,6 +20,12 @@
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
; RUN: -mcpu=mips32r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-PIC
+; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
+; RUN: -mattr=+micromips < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC
+; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
+; RUN: -mattr=+micromips < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC
; Check again for big-endian
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
@@ -27,6 +37,12 @@
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
; RUN: -mcpu=mips32r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-BE,32R6-BE-PIC
+; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
+; RUN: -mattr=+micromips < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC
+; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
+; RUN: -mattr=+micromips < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC
; Check again for the static relocation model
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
@@ -38,6 +54,10 @@
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
; RUN: -mcpu=mips32r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \
+; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC_PIC
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
+; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC
@g0 = common global double 0.000000e+00, align 8
@@ -100,6 +120,26 @@
; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
+; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM: ldc1 $f0, 0($[[R3]])
+
+; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]])
+; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]])
+; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0
+; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0
+; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0
+; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0
+
+; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)
+; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]])
+
define double @test_ldc1() {
entry:
%0 = load double, double* @g0, align 8
@@ -165,6 +205,26 @@ entry:
; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
+; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM: sdc1 $f12, 0($[[R3]])
+
+; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25
+; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]])
+; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]])
+; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]])
+
+; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)
+; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]])
+
define void @test_sdc1(double %a) {
entry:
store double %a, double* @g0, align 8
@@ -201,6 +261,23 @@ entry:
; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
+; MM: sll16 $[[R0:[0-9]+]], $5, 3
+; MM: addu16 $[[R1:[0-9]+]], $4, $[[R0]]
+; MM: ldc1 $f0, 0($[[R1]])
+
+; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3
+; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]]
+; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]])
+; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]])
+; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0
+; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0
+; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0
+; MM-MNO-BE-PIC: mthc1 $[[R2]], $f0
+
+; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3
+; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]]
+; MM-STATIC-PIC: ldc1 $f0, 0($[[R1]])
+
define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double, double* %a, i32 %i
@@ -232,6 +309,23 @@ entry:
; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
+; MM: sll16 $[[R0:[0-9]+]], $7, 3
+; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
+; MM: sdc1 $f12, 0($[[R1]])
+
+; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3
+; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
+; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]])
+; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]])
+
+; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3
+; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
+; MM-STATIC-PIC: sdc1 $f12, 0($[[R1]])
+
define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double, double* %a, i32 %i
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Mon Jul 11 02:41:56 2016
@@ -189,3 +189,9 @@
0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
0x00 0x00 0x7c 0x8b # CHECK: syscall
0x8c 0x01 0x7c 0x8b # CHECK: syscall 396
+0xea 0xbc 0x2c 0x01 # CHECK: ldc1 $f7, 300($10)
+0x0a 0xbd 0x2c 0x01 # CHECK: ldc1 $f8, 300($10)
+0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6)
+0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
+0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
+0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Mon Jul 11 02:41:56 2016
@@ -189,3 +189,9 @@
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
+0xbc 0xea 0x01 0x2c # CHECK: ldc1 $f7, 300($10)
+0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
+0x9c 0x46 0x00 0x04 # CHECK: lwc1 $f2, 4($6)
+0xb8 0x46 0x00 0x04 # CHECK: sdc1 $f2, 4($6)
+0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10)
+0x98 0x46 0x00 0x04 # CHECK: swc1 $f2, 4($6)
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Mon Jul 11 02:41:56 2016
@@ -325,3 +325,13 @@
0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5
0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5
0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4
+0xbc 0xea 0x01 0x2c # CHECK: ldc1 $f7, 300($10)
+0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
+0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
+0x9c 0x45 0x00 0x20 # CHECK: lwc1 $f2, 32($5)
+0x20 0x24 0x00 0x10 # CHECK: lwc2 $1, 16($4)
+0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10)
+0xb9 0x0a 0x00 0x40 # CHECK: sdc1 $f8, 64($10)
+0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16)
+0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13)
+0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17)
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Mon Jul 11 02:41:56 2016
@@ -296,3 +296,13 @@
0x58 0x22 0x10 0x40 # CHECK: dsrl $1, $2, 2
0x58 0x64 0x28 0x48 # CHECK: dsrl32 $3, $4, 5
0x58 0x63 0x08 0x50 # CHECK: dsrlv $1, $3, $3
+0xbc 0xea 0x01 0x2c # CHECK: ldc1 $f7, 300($10)
+0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
+0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
+0x9c 0x45 0x00 0x20 # CHECK: lwc1 $f2, 32($5)
+0x20 0x24 0x00 0x10 # CHECK: lwc2 $1, 16($4)
+0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10)
+0xb9 0x0a 0x00 0x40 # CHECK: sdc1 $f8, 64($10)
+0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16)
+0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13)
+0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17)
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Mon Jul 11 02:41:56 2016
@@ -120,3 +120,11 @@
xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -28,3 +28,17 @@
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ lwc2 $1, -2049($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 2048($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 16($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ swc2 $1, -2049($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Mon Jul 11 02:41:56 2016
@@ -249,3 +249,35 @@
xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Mon Jul 11 02:41:56 2016
@@ -354,3 +354,13 @@
or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05]
xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05]
xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05]
+ ldc1 $f7, 300($10) # CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
+ ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
+ ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff]
+ lwc1 $f2, 32($5) # CHECK: lwc1 $f2, 32($5) # encoding: [0x9c,0x45,0x00,0x20]
+ lwc2 $1, 16($4) # CHECK: lwc2 $1, 16($4) # encoding: [0x20,0x24,0x00,0x10]
+ sdc1 $f7, 64($10) # CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40]
+ sdc1 $f8, 64($10) # CHECK: sdc1 $f8, 64($10) # encoding: [0xb9,0x0a,0x00,0x40]
+ sdc2 $2, 8($16) # CHECK: sdc2 $2, 8($16) # encoding: [0x20,0x50,0xa0,0x08]
+ swc1 $f6, 369($13) # CHECK: swc1 $f6, 369($13) # encoding: [0x98,0xcd,0x01,0x71]
+ swc2 $7, 777($17) # CHECK: swc2 $7, 777($17) # encoding: [0x20,0xf1,0x83,0x09]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -38,3 +38,15 @@
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ lwc2 $1, -2049($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 2048($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 16($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
+ swc2 $1, -2049($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Mon Jul 11 02:41:56 2016
@@ -297,3 +297,31 @@
sd $31, 65536($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
sd $31, 32768($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
sd $31, -32769($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Mon Jul 11 02:41:56 2016
@@ -307,5 +307,15 @@ a:
dsrl $1, $2, 2 # CHECK: dsrl $1, $2, 2 # encoding: [0x58,0x22,0x10,0x40]
dsrl32 $3, $4, 5 # CHECK: dsrl32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x48]
dsrlv $1, $3, $3 # CHECK: dsrlv $1, $3, $3 # encoding: [0x58,0x63,0x08,0x50]
+ ldc1 $f7, 300($10) # CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
+ ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
+ ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff]
+ lwc1 $f2, 32($5) # CHECK: lwc1 $f2, 32($5) # encoding: [0x9c,0x45,0x00,0x20]
+ lwc2 $1, 16($4) # CHECK: lwc2 $1, 16($4) # encoding: [0x20,0x24,0x00,0x10]
+ sdc1 $f7, 64($10) # CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40]
+ sdc1 $f8, 64($10) # CHECK: sdc1 $f8, 64($10) # encoding: [0xb9,0x0a,0x00,0x40]
+ sdc2 $2, 8($16) # CHECK: sdc2 $2, 8($16) # encoding: [0x20,0x50,0xa0,0x08]
+ swc1 $f6, 369($13) # CHECK: swc1 $f6, 369($13) # encoding: [0x98,0xcd,0x01,0x71]
+ swc2 $7, 777($17) # CHECK: swc2 $7, 777($17) # encoding: [0x20,0xf1,0x83,0x09]
1:
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -6,13 +6,11 @@
# RUN: FileCheck %s < %t1
.set noat
- ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
- sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -6,7 +6,6 @@
# RUN: FileCheck %s < %t1
.set noat
- ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -14,7 +13,6 @@
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
- sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -8,7 +8,6 @@
.set noat
bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -16,7 +15,6 @@
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
- sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s Mon Jul 11 02:41:56 2016
@@ -88,3 +88,5 @@
sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+ sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/mips32r5/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/invalid.s Mon Jul 11 02:41:56 2016
@@ -20,3 +20,49 @@
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+ lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc2 $1, -32769($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ ldc2 $1, 32768($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc2 $1, -32769($16) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $1, 32768($16) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $1, 8($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc2 $1, -32769($4) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $1, 32768($4) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $1, 16($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc2 $1, -32769($17) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $1, 32768($17) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $1, 777($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s Mon Jul 11 02:41:56 2016
@@ -9,3 +9,15 @@
bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
+ ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $1, -2049($4) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 2048($4) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ lwc2 $1, 16($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ sdc2 $1, 8($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $1, -2049($17) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 2048($17) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ swc2 $1, 777($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid.s Mon Jul 11 02:41:56 2016
@@ -85,3 +85,39 @@ local_label:
sdc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
sync -1 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
sync 32 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+ lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips64r5/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/invalid.s Mon Jul 11 02:41:56 2016
@@ -19,3 +19,49 @@
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc2 $1, -32769($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ ldc2 $1, 32768($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc2 $1, -32769($16) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $1, 32768($16) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ sdc2 $1, 8($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc2 $1, -32769($4) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $1, 32768($4) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $1, 16($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc2 $1, -32769($17) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $1, 32768($17) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ swc2 $1, 777($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+ lwc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s Mon Jul 11 02:41:56 2016
@@ -93,3 +93,39 @@ local_label:
dsrl32 $32, $32, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dsrlv $2, $4, 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dsrlv $32, $32, $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ lb $4, -32769($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 32768($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lb $4, 8($32) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+ lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+ lbu $4, -32769($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 32768($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ lbu $4, 8($32) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+ ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ swc1 $f6, 369($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+ ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/target-soft-float.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/target-soft-float.s?rev=275050&r1=275049&r2=275050&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/target-soft-float.s (original)
+++ llvm/trunk/test/MC/Mips/target-soft-float.s Mon Jul 11 02:41:56 2016
@@ -269,10 +269,10 @@ foo:
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
ldc1 $f2, 16($7)
# FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
- # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+ # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
lwc1 $f2, 16($7)
# FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
- # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+ # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
madd.s $f2, $f2, $f2, $f2
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
mfc1 $7, $f2
@@ -313,7 +313,7 @@ foo:
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
sdc1 $f2, 16($7)
# FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
- # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+ # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
sqrt.d $f2, $f2
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
sqrt.s $f2, $f2
@@ -324,7 +324,7 @@ foo:
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
swc1 $f2, 16($7)
# FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
- # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+ # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
trunc.w.d $f2, $f2
# 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f2, $f2
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