[llvm] r275028 - [X86][SSE] Relax type assertions for matchVectorShuffleAsInsertPS

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Jul 10 17:26:05 2016
New Revision: 275028

URL: http://llvm.org/viewvc/llvm-project?rev=275028&view=rev
Log:
[X86][SSE] Relax type assertions for matchVectorShuffleAsInsertPS

Calls to matchVectorShuffleAsInsertPS only need to ensure the inputs are 128-bit vectors. Only lowerVectorShuffleAsInsertPS needs to ensure that they are v4f32.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=275028&r1=275027&r2=275028&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 10 17:26:05 2016
@@ -8692,8 +8692,8 @@ static bool matchVectorShuffleAsInsertPS
                                          const SmallBitVector &Zeroable,
                                          ArrayRef<int> Mask,
                                          SelectionDAG &DAG) {
-  assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
-  assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
+  assert(V1.getSimpleValueType().is128BitVector() && "Bad operand type!");
+  assert(V2.getSimpleValueType().is128BitVector() && "Bad operand type!");
   assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
   unsigned ZMask = 0;
   int V1DstIndex = -1;
@@ -8757,6 +8757,8 @@ static bool matchVectorShuffleAsInsertPS
 static SDValue lowerVectorShuffleAsInsertPS(const SDLoc &DL, SDValue V1,
                                             SDValue V2, ArrayRef<int> Mask,
                                             SelectionDAG &DAG) {
+  assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
+  assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
   SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
 
   // Attempt to match the insertps pattern.