[llvm] r274980 - [lanai] Treat .t as optional in assembly parser for RR operands and add predicate operand to ShiftRR
Jacques Pienaar via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 9 11:26:05 PDT 2016
Author: jpienaar
Date: Sat Jul 9 13:26:04 2016
New Revision: 274980
URL: http://llvm.org/viewvc/llvm-project?rev=274980&view=rev
Log:
[lanai] Treat .t as optional in assembly parser for RR operands and add predicate operand to ShiftRR
Modified:
llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
llvm/trunk/test/MC/Lanai/v11.s
Modified: llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp?rev=274980&r1=274979&r2=274980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp Sat Jul 9 13:26:04 2016
@@ -1112,6 +1112,27 @@ bool IsMemoryAssignmentError(const Opera
Operands[PossibleDestIdx]->getReg();
}
+static bool IsRegister(const MCParsedAsmOperand &op) {
+ return static_cast<const LanaiOperand &>(op).isReg();
+}
+
+static bool MaybePredicatedInst(const OperandVector &Operands) {
+ if (Operands.size() < 4 || !IsRegister(*Operands[1]) ||
+ !IsRegister(*Operands[2]))
+ return false;
+ return StringSwitch<bool>(
+ static_cast<const LanaiOperand &>(*Operands[0]).getToken())
+ .StartsWith("addc", true)
+ .StartsWith("add", true)
+ .StartsWith("and", true)
+ .StartsWith("sh", true)
+ .StartsWith("subb", true)
+ .StartsWith("sub", true)
+ .StartsWith("or", true)
+ .StartsWith("xor", true)
+ .Default(false);
+}
+
bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
@@ -1164,6 +1185,15 @@ bool LanaiAsmParser::ParseInstruction(Pa
return true;
}
+ // Insert always true operand for instruction that may be predicated but
+ // are not. Currently the autogenerated parser always expects a predicate.
+ if (MaybePredicatedInst(Operands)) {
+ Operands.insert(Operands.begin() + 1,
+ LanaiOperand::createImm(
+ MCConstantExpr::create(LPCC::ICC_T, getContext()),
+ NameLoc, NameLoc));
+ }
+
return false;
}
Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td?rev=274980&r1=274979&r2=274980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td Sat Jul 9 13:26:04 2016
@@ -443,31 +443,30 @@ let F = 1, Defs = [SR] in {
}
class ShiftRR<string AsmStr, list<dag> Pattern>
- : InstRR<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2), AsmStr, Pattern> {
- let DDDI = 0;
-}
+ : InstRR<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI), AsmStr,
+ Pattern>;
let F = 0 in {
let JJJJJ = 0b10000 in
- def SHL_R : ShiftRR<"sh\t$Rs1, $Rs2, $Rd",
+ def SHL_R : ShiftRR<"sh$DDDI\t$Rs1, $Rs2, $Rd",
[(set GPR:$Rd, (shl GPR:$Rs1, GPR:$Rs2))]>;
let isCodeGenOnly = 1 in {
let JJJJJ = 0b10000 in
- def SRL_R : ShiftRR<"sh\t$Rs1, $Rs2, $Rd", []>;
+ def SRL_R : ShiftRR<"sh$DDDI\t$Rs1, $Rs2, $Rd", []>;
}
let JJJJJ = 0b11000 in
- def SRA_R : ShiftRR<"sha\t$Rs1, $Rs2, $Rd", []>;
+ def SRA_R : ShiftRR<"sha$DDDI\t$Rs1, $Rs2, $Rd", []>;
}
let F = 1, Defs = [SR] in {
let JJJJJ = 0b10000 in
- def SHL_F_R : ShiftRR<"sh.f\t$Rs1, $Rs2, $Rd", []>;
+ def SHL_F_R : ShiftRR<"sh.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
let isCodeGenOnly = 1 in {
let JJJJJ = 0b10000 in
- def SRL_F_R : ShiftRR<"sh.f\t$Rs1, $Rs2, $Rd", []>;
+ def SRL_F_R : ShiftRR<"sh.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
}
let JJJJJ = 0b11000 in
- def SRA_F_R : ShiftRR<"sha.f\t$Rs1, $Rs2, $Rd", []>;
+ def SRA_F_R : ShiftRR<"sha.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
}
// Expand shift-right operations
Modified: llvm/trunk/test/MC/Lanai/v11.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Lanai/v11.s?rev=274980&r1=274979&r2=274980&view=diff
==============================================================================
--- llvm/trunk/test/MC/Lanai/v11.s (original)
+++ llvm/trunk/test/MC/Lanai/v11.s Sat Jul 9 13:26:04 2016
@@ -12,13 +12,13 @@ add.f %r17, 0x00001234, %r21
! CHECK: 0x0a,0xc6,0x12,0x34
add.f %r17, 0x12340000, %r21
! CHECK: 0x0a,0xc7,0x12,0x34
-add.t %r17, %r18, %r21
+add %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x90,0x00
-add.f.t %r17, %r18, %r21
+add.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x90,0x00
-addc.t %r17, %r18, %r21
+addc %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x91,0x00
-addc.f.t %r17, %r18, %r21
+addc.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x91,0x00
addc %r17, 0, %r21
! CHECK: 0x1a,0xc4,0x00,0x00
@@ -40,9 +40,9 @@ and.f %r17, 0xffff1234, %r21
! CHECK: 0x4a,0xc6,0x12,0x34
and.f %r17, 0x1234ffff, %r21
! CHECK: 0x4a,0xc7,0x12,0x34
-and.t %r17, %r18, %r21
+and %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x94,0x00
-and.f.t %r17, %r18, %r21
+and.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x94,0x00
bt 0x123454
! CHECK: 0xe0,0x12,0x34,0x54
@@ -418,9 +418,9 @@ or.f %r17, 0x00001234, %r21
! CHECK: 0x5a,0xc6,0x12,0x34
or.f %r17, 0x12340000, %r21
! CHECK: 0x5a,0xc7,0x12,0x34
-or.t %r17, %r18, %r21
+or %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x95,0x00
-or.f.t %r17, %r18, %r21
+or.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x95,0x00
popc %r17, %r21
! CHECK: 0xda,0xc4,0x00,0x01
@@ -790,9 +790,9 @@ sub.f %r17, 0x00001234, %r21
! CHECK: 0x2a,0xc6,0x12,0x34
sub.f %r17, 0x12340000, %r21
! CHECK: 0x2a,0xc7,0x12,0x34
-sub.t %r17, %r18, %r21
+sub %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x92,0x00
-sub.f.t %r17, %r18, %r21
+sub.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x92,0x00
subb %r17, 0, %r21
! CHECK: 0x3a,0xc4,0x00,0x00
@@ -806,9 +806,9 @@ subb.f %r17, 0x00001234, %r21
! CHECK: 0x3a,0xc6,0x12,0x34
subb.f %r17, 0x12340000, %r21
! CHECK: 0x3a,0xc7,0x12,0x34
-subb.t %r17, %r18, %r21
+subb %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x93,0x00
-subb.f.t %r17, %r18, %r21
+subb.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x93,0x00
xor %r17, 0, %r21
! CHECK: 0x6a,0xc4,0x00,0x00
@@ -822,9 +822,9 @@ xor.f %r17, 0x00001234, %r21
! CHECK: 0x6a,0xc6,0x12,0x34
xor.f %r17, 0x12340000, %r21
! CHECK: 0x6a,0xc7,0x12,0x34
-xor.t %r17, %r18, %r21
+xor %r17, %r18, %r21
! CHECK: 0xca,0xc4,0x96,0x00
-xor.f.t %r17, %r18, %r21
+xor.f %r17, %r18, %r21
! CHECK: 0xca,0xc6,0x96,0x00
sel.ne %r9, %r15, %r12
! CHECK: 0xc6,0x24,0x7f,0x03
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