[llvm] r274937 - Reapply r274829 with fix for FP vectors

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri Jul  8 16:25:33 2016
New Revision: 274937

URL: http://llvm.org/viewvc/llvm-project?rev=274937&view=rev
Log:
Reapply r274829 with fix for FP vectors

Added:
    llvm/trunk/test/CodeGen/X86/pr28444.ll
    llvm/trunk/test/CodeGen/X86/pr28472.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/AMDGPU/vector-extract-insert.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=274937&r1=274936&r2=274937&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jul  8 16:25:33 2016
@@ -12407,8 +12407,10 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR
   // This only really matters if the index is non-constant since other combines
   // on the constant elements already work.
   if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT &&
-      EltNo == InVec.getOperand(2))
-    return InVec.getOperand(1);
+      EltNo == InVec.getOperand(2)) {
+    SDValue Elt = InVec.getOperand(1);
+    return VT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, SDLoc(N), NVT) : Elt;
+  }
 
   // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
   // We only perform this optimization before the op legalization phase because

Modified: llvm/trunk/test/CodeGen/AMDGPU/vector-extract-insert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vector-extract-insert.ll?rev=274937&r1=274936&r2=274937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vector-extract-insert.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vector-extract-insert.ll Fri Jul  8 16:25:33 2016
@@ -61,6 +61,24 @@ define void @extract_insert_same_elt2_v4
   ret void
 }
 
+; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4f32:
+; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}}
+; GCN-NOT buffer_load_dword
+; GCN-NOT: [[VAL]]
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN-NOT: [[VVAL]]
+; GCN: buffer_store_dword [[VVAL]]
+define void @extract_insert_same_dynelt_v4f32(float addrspace(1)* %out, <4 x float> addrspace(1)* %in, float %val, i32 %idx) #1 {
+  %id = call i32 @llvm.amdgcn.workitem.id.x()
+  %id.ext = sext i32 %id to i64
+  %gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext
+  %gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext
+  %vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in
+  %insert = insertelement <4 x float> %vec, float %val, i32 %idx
+  %extract = extractelement <4 x float> %insert, i32 %idx
+  store float %extract, float addrspace(1)* %gep.out
+  ret void
+}
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
\ No newline at end of file

Added: llvm/trunk/test/CodeGen/X86/pr28444.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr28444.ll?rev=274937&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr28444.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr28444.ll Fri Jul  8 16:25:33 2016
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 < %s | FileCheck %s
+; https://llvm.org/bugs/show_bug.cgi?id=28444
+
+; extract_vector_elt is allowed to have a different result type than
+; the vector scalar type.
+; This uses both
+;  i8 = extract_vector_elt v1i1, Constant:i64<0>
+;  i1 = extract_vector_elt v1i1, Constant:i64<0>
+
+
+; CHECK-LABEL: {{^}}extractelt_mismatch_vector_element_type:
+; CHECK: movb $1, %al
+; CHECK: movb %al
+; CHECK: movb %al
+define void @extractelt_mismatch_vector_element_type(i32 %arg) {
+bb:
+  %tmp = icmp ult i32 %arg, 0
+  %tmp2 = insertelement <1 x i1> undef, i1 true, i32 0
+  %tmp3 = select i1 %tmp, <1 x i1> undef, <1 x i1> %tmp2
+  %tmp6 = extractelement <1 x i1> %tmp3, i32 0
+  br label %bb1
+
+bb1:
+  store volatile <1 x i1> %tmp3, <1 x i1>* undef
+  store volatile i1 %tmp6, i1* undef
+  ret void
+}

Added: llvm/trunk/test/CodeGen/X86/pr28472.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr28472.ll?rev=274937&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr28472.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr28472.ll Fri Jul  8 16:25:33 2016
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; CHECK-LABEL: {{^}}same_dynamic_index_fp_vector_type:
+; CHECK: # BB#0:
+; CHECK-NEXT: retq
+define float @same_dynamic_index_fp_vector_type(float %val, i32 %idx) {
+bb:
+  %tmp0 = insertelement <4 x float> undef, float %val, i32 %idx
+  %tmp1 = extractelement <4 x float> %tmp0, i32 %idx
+  ret float %tmp1
+}