[llvm] r274852 - [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)

[Valery Pykhtin via llvm-commits]

Author: vpykhtin
Date: Fri Jul  8 10:12:46 2016
New Revision: 274852

URL: http://llvm.org/viewvc/llvm-project?rev=274852&view=rev
Log:
[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)

Differential Revision: http://reviews.llvm.org/D22049

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
    llvm/trunk/test/MC/AMDGPU/ds.s
    llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=274852&r1=274851&r2=274852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Fri Jul  8 10:12:46 2016
@@ -69,6 +69,11 @@ class sopk <bits<5> si, bits<5> vi = si>
   field bits<5> VI = vi;
 }
 
+class dsop <bits<8> si, bits<8> vi = si> {
+  field bits<8> SI = si;
+  field bits<8> VI = vi;
+}
+
 // Specify an SMRD opcode for SI and SMEM opcode for VI
 
 // FIXME: This should really be bits<5> si, Tablegen crashes if
@@ -2591,6 +2596,21 @@ class DS_Off16_Real_vi <bits<8> op, stri
   let offset1 = offset{15-8};
 }
 
+multiclass DS_1A_RET_ <dsop op, string opName, RegisterClass rc,
+  dag outs = (outs rc:$vdst),
+  dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
+  string asm = opName#" $vdst, $addr"#"$offset$gds"> {
+
+  def "" : DS_Pseudo <opName, outs, ins, []>;
+
+  let data0 = 0, data1 = 0 in {
+    def _si : DS_Off16_Real_si <op.SI, opName, outs, ins, asm>;
+    def _vi : DS_Off16_Real_vi <op.VI, opName, outs, ins, asm>;
+  }
+}
+
+// TODO: DS_1A_RET can be inherited from DS_1A_RET_ but its not working
+// for some reason. In fact we can remove this class if use dsop everywhere
 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
   dag outs = (outs rc:$vdst),
   dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=274852&r1=274851&r2=274852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Fri Jul  8 10:12:46 2016
@@ -825,7 +825,7 @@ defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32,
 defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
 
 let Uses = [EXEC], mayLoad =0, mayStore = 0, isConvergent = 1 in {
-defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>;
+defm DS_SWIZZLE_B32 : DS_1A_RET_ <dsop<0x35, 0x3d>, "ds_swizzle_b32", VGPR_32>;
 }
 
 let mayStore = 0 in {

Modified: llvm/trunk/test/MC/AMDGPU/ds.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds.s?rev=274852&r1=274851&r2=274852&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds.s Fri Jul  8 10:12:46 2016
@@ -240,7 +240,7 @@ ds_max_rtn_f32 v8, v2, v4, v6
 
 ds_swizzle_b32 v8, v2
 // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
-// VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
+// VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 
 ds_read_b32 v8, v2
 // SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt?rev=274852&r1=274851&r2=274852&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt Fri Jul  8 10:12:46 2016
@@ -162,8 +162,8 @@
 # VI:   ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
 0x00 0x00 0x66 0xd8 0x02 0x04 0x06 0x08
 
-# VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
-0x00 0x00 0x6a 0xd8 0x02 0x00 0x00 0x08
+# VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
+0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08