[llvm] r274843 - Code size optimisation: don't expand a div to a mul and and a shift sequence.

[Benjamin Kramer via llvm-commits]

On Fri, Jul 8, 2016 at 2:54 PM, Sjoerd Meijer via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: sjoerdmeijer
> Date: Fri Jul  8 07:54:43 2016
> New Revision: 274843
>
> URL: http://llvm.org/viewvc/llvm-project?rev=274843&view=rev
> Log:
> Code size optimisation: don't expand a div to a mul and and a shift sequence.
> As a result, the urem instruction will not be expanded to a sequence of umull,
> lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod.

This has historically been one of the things that we intentionally
didn't do at -Os because it can significantly affect runtime with only
a minor gain in code size, especially when there is no hardware div
available. I'm still not sure that this is a good fit for -Os, and
would prefer if we did it for -Oz only. Does that still solve your use
case?

>
> Differential Revision: http://reviews.llvm.org/D22131
>
> Added:
>     llvm/trunk/test/CodeGen/ARM/urem-opt-size.ll
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=274843&r1=274842&r2=274843&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jul  8 07:54:43 2016
> @@ -14516,6 +14516,11 @@ SDValue DAGCombiner::BuildSDIVPow2(SDNod
>  /// number.
>  /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
>  SDValue DAGCombiner::BuildUDIV(SDNode *N) {
> +  // when optimising for size, we don't want to expand a div to a mul and
> +  // and a shift.
> +  if (ForCodeSize)
> +    return SDValue();
> +
>    ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
>    if (!C)
>      return SDValue();
>
> Added: llvm/trunk/test/CodeGen/ARM/urem-opt-size.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/urem-opt-size.ll?rev=274843&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/urem-opt-size.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/urem-opt-size.ll Fri Jul  8 07:54:43 2016
> @@ -0,0 +1,25 @@
> +; When optimising for size, we don't want to expand a div to a mul and
> +; and a shift sequence. As a result, the urem instruction will not be
> +; expanded to a sequence of umull, lsrs, muls and sub instructions, but
> +; just a call to __aeabi_uidivmod.
> +;
> +; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | FileCheck %s
> +
> +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
> +target triple = "thumbv7m-arm-none-eabi"
> +
> +define i32 @foo() local_unnamed_addr #0 {
> +entry:
> +; CHECK-LABEL: foo:
> +; CHECK: __aeabi_uidivmod
> +; CHECK-NOT: umull
> +  %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
> +  %rem = urem i32 %call, 1000000
> +  %cmp = icmp eq i32 %rem, 0
> +  %conv = zext i1 %cmp to i32
> +  ret i32 %conv
> +}
> +
> +declare i32 @GetValue(...) local_unnamed_addr
> +
> +attributes #0 = { minsize nounwind optsize }
>
>
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