[llvm] r274815 - ARM: support high registers in __builtin_longjmp on WoA
Saleem Abdulrasool via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 7 17:48:22 PDT 2016
Author: compnerd
Date: Thu Jul 7 19:48:22 2016
New Revision: 274815
URL: http://llvm.org/viewvc/llvm-project?rev=274815&view=rev
Log:
ARM: support high registers in __builtin_longjmp on WoA
Windows on ARM uses a pure thumb-2 environment. This means that it can select a
high register when doing a __builtin_longjmp. We would use a tLDRi which would
truncate the register to a low register. Use a t2LDRi12 to get the full
register file access. Tweak the code to just load into PC, as that is an
interworking branch on all supported cores anyways.
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/test/CodeGen/ARM/Windows/builtin_longjmp.ll
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=274815&r1=274814&r2=274815&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jul 7 19:48:22 2016
@@ -1882,8 +1882,7 @@ void ARMAsmPrinter::EmitInstruction(cons
.addReg(0));
return;
}
- case ARM::tInt_eh_sjlj_longjmp:
- case ARM::tInt_WIN_eh_sjlj_longjmp: {
+ case ARM::tInt_eh_sjlj_longjmp: {
// ldr $scratch, [$src, #8]
// mov sp, $scratch
// ldr $scratch, [$src, #4]
@@ -1918,7 +1917,7 @@ void ARMAsmPrinter::EmitInstruction(cons
.addReg(0));
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
- .addReg(Opc == ARM::tInt_WIN_eh_sjlj_longjmp ? ARM::R11 : ARM::R7)
+ .addReg(ARM::R7)
.addReg(SrcReg)
.addImm(0)
// Predicate.
@@ -1932,6 +1931,36 @@ void ARMAsmPrinter::EmitInstruction(cons
.addReg(0));
return;
}
+ case ARM::tInt_WIN_eh_sjlj_longjmp: {
+ // ldr.w r11, [$src, #0]
+ // ldr.w sp, [$src, #8]
+ // ldr.w pc, [$src, #4]
+
+ unsigned SrcReg = MI->getOperand(0).getReg();
+
+ EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
+ .addReg(ARM::R11)
+ .addReg(SrcReg)
+ .addImm(0)
+ // Predicate
+ .addImm(ARMCC::AL)
+ .addReg(0));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
+ .addReg(ARM::SP)
+ .addReg(SrcReg)
+ .addImm(8)
+ // Predicate
+ .addImm(ARMCC::AL)
+ .addReg(0));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
+ .addReg(ARM::PC)
+ .addReg(SrcReg)
+ .addImm(4)
+ // Predicate
+ .addImm(ARMCC::AL)
+ .addReg(0));
+ return;
+ }
}
MCInst TmpInst;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=274815&r1=274814&r2=274815&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul 7 19:48:22 2016
@@ -648,8 +648,9 @@ unsigned ARMBaseInstrInfo::GetInstSizeIn
case ARM::Int_eh_sjlj_longjmp:
return 16;
case ARM::tInt_eh_sjlj_longjmp:
- case ARM::tInt_WIN_eh_sjlj_longjmp:
return 10;
+ case ARM::tInt_WIN_eh_sjlj_longjmp:
+ return 12;
case ARM::Int_eh_sjlj_setjmp:
case ARM::Int_eh_sjlj_setjmp_nofp:
return 20;
Modified: llvm/trunk/test/CodeGen/ARM/Windows/builtin_longjmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/Windows/builtin_longjmp.ll?rev=274815&r1=274814&r2=274815&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/builtin_longjmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/Windows/builtin_longjmp.ll Thu Jul 7 19:48:22 2016
@@ -9,9 +9,7 @@ entry:
}
; CHECK: push.w {r11, lr}
-; CHECK: ldr r[[SP:[0-9]+]], [r0, #8]
-; CHECK: mov sp, r[[SP]]
-; CHECK: ldr r[[PC:[0-9]+]], [r0, #4]
-; CHECK: ldr r11, [r0]
-; CHECK: bx r[[PC]]
+; CHECK: ldr.w r11, [r0]
+; CHECK: ldr.w sp, [r0, #8]
+; CHECK: ldr.w pc, [r0, #4]
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