[PATCH] D19825: Power9 - Add exploitation of vector load and store that do not require swaps

[Eric Christopher via llvm-commits]

echristo added a comment.

Couple more inline comments... I'm just coming up to speed on the new vector stuff so excuse any obvious questions :)


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:10554
@@ -10550,3 +10553,3 @@
       MVT StoreVT = VT.getSimpleVT();
-      if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
+      if (NeedsSwapsForVSXMemOps &&
           (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
----------------
nemanjai wrote:
> echristo wrote:
> > Would it make sense for this to be a subtarget feature given all of the load/store instruction changes for vectors? Though I guess you couldn't just use Subtarget.isISA3_0 anymore as the canonical "am I targeting something P9 or later".
> > 
> > 
> I can certainly define something like HasNonPermutingMemOps in PPC.td and make it part of the Power9 processor definition. The only reason it hasn't been defined is that we kind of decided not to have too much granularity with Power9 since there are no optional features. But if you feel that it might be useful to be able to turn this off and turn on the rest of the Power9 instructions, I can certainly do that.
Actually, you should probably just make it a PPCSubtarget routine, don't worry about the feature aspect - as you say, we don't need to worry about separating it out.

That way you can use the simple query all over the place.

================
Comment at: lib/Target/PowerPC/PPCInstrInfo.cpp:1009
@@ -1006,2 +1008,3 @@
   } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
+    unsigned Op = Subtarget.isISA3_0() ? PPC::STXVX : PPC::STXVD2X;
+    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
----------------
... including here I imagine.

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2161
@@ +2160,3 @@
+
+  let AddedComplexity = 500 in {
+    def : Pat<(v2f64 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
----------------
Can we just exclude the other patterns? We don't ever want them to show up do we?


Repository:
  rL LLVM

http://reviews.llvm.org/D19825