[PATCH] D21998: [AArch64] Fix assert failure with indexed loads.

[Ismail Badawi via llvm-commits]

ibadawi created this revision.
ibadawi added a reviewer: t.p.northover.
ibadawi added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

We take the 0th result from OrOpd0, which is not necessarily correct if it
produces multiple results -- for example, in this new test case, OrOpd0 is an
indexed load, and we want the 1st result.

Fix by remembering the original SDValue instead of making a new one.

n.b. This is a fix for this assert failure:

llc: /scratch/2/llvm-upstream/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1993: bool isBitfieldPositioningOp(llvm::SelectionDAG*, llvm::SDValue, bool, llvm::SDValue&, int&, int&): Assertion `BitWidth == 32 || BitWidth == 64' failed.
...snip...
#9 0x0000000000f7bf97 isBitfieldPositioningOp(llvm::SelectionDAG*, llvm::SDValue, bool, llvm::SDValue&, int&, int&) /scratch/2/llvm-upstream/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1995:0
#10 0x0000000000f7cdbd tryBitfieldInsertOpFromOr(llvm::SDNode*, llvm::APInt const&, llvm::SelectionDAG*) /scratch/2/llvm-upstream/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2200:0

http://reviews.llvm.org/D21998

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll

Index: test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll
@@ -0,0 +1,36 @@
+; RUN: llc <%s
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+; Function Attrs: noreturn nounwind
+define void @foo(i32* %d) {
+entry:
+  %0 = ptrtoint i32* %d to i64
+  %1 = and i64 %0, -36028797018963969
+  %2 = inttoptr i64 %1 to i32*
+  %arrayidx5 = getelementptr inbounds i32, i32* %2, i64 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %2, i64 2
+  %arrayidx7 = getelementptr inbounds i32, i32* %2, i64 3
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond, %entry
+  %B.0 = phi i32* [ %d, %entry ], [ %12, %for.cond ]
+  %3 = ptrtoint i32* %B.0 to i64
+  %4 = and i64 %3, -36028797018963969
+  %5 = inttoptr i64 %4 to i32*
+  %6 = load i32, i32* %5, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %5, i64 1
+  %7 = load i32, i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %5, i64 2
+  %8 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %5, i64 3
+  %9 = load i32, i32* %arrayidx3, align 4
+  store i32 %6, i32* %2, align 4
+  store i32 %7, i32* %arrayidx5, align 4
+  store i32 %8, i32* %arrayidx6, align 4
+  store i32 %9, i32* %arrayidx7, align 4
+  %10 = ptrtoint i32* %arrayidx1 to i64
+  %11 = or i64 %10, 36028797018963968
+  %12 = inttoptr i64 %11 to i32*
+  br label %for.cond
+}
Index: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2172,7 +2172,8 @@
     SDValue Dst, Src;
     unsigned ImmR, ImmS;
     bool BiggerPattern = I / 2;
-    SDNode *OrOpd0 = N->getOperand(I % 2).getNode();
+    SDValue OrOpd0Val = N->getOperand(I % 2);
+    SDNode *OrOpd0 = OrOpd0Val.getNode();
     SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
     SDNode *OrOpd1 = OrOpd1Val.getNode();
 
@@ -2197,7 +2198,7 @@
 
       // If the mask on the insertee is correct, we have a BFXIL operation. We
       // can share the ImmR and ImmS values from the already-computed UBFM.
-    } else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0),
+    } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
                                        BiggerPattern,
                                        Src, DstLSB, Width)) {
       ImmR = (BitWidth - DstLSB) % BitWidth;


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