[PATCH] D21481: ELF/AMDGPU: Add support for GOT relocations

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL274514: ELF/AMDGPU: Add support for GOT relocations (authored by tstellar).

Changed prior to commit:
  http://reviews.llvm.org/D21481?vs=61801&id=62706#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D21481

Files:
  lld/trunk/ELF/Target.cpp
  lld/trunk/test/ELF/amdgpu-relocs.s

Index: lld/trunk/test/ELF/amdgpu-relocs.s
===================================================================
--- lld/trunk/test/ELF/amdgpu-relocs.s
+++ lld/trunk/test/ELF/amdgpu-relocs.s
@@ -4,15 +4,30 @@
 
 # REQUIRES: amdgpu
 
-# Make sure that the reloc for local_var is resolved by lld.
-
   .text
 
 kernel0:
+  s_mov_b32 s0, common_var at GOTPCREL+4
+  s_mov_b32 s0, extern_var at GOTPCREL+4
   s_mov_b32 s0, local_var+4
+  s_mov_b32 s0, global_var at GOTPCREL+4
+  s_mov_b32 s0, weak_var at GOTPCREL+4
+  s_mov_b32 s0, weakref_var at GOTPCREL+4
   s_endpgm
 
-  .local local_var
+  .comm   common_var,1024,4
+  .globl  global_var
+  .local  local_var
+  .weak   weak_var
+  .weakref weakref_var, weakref_alias_var
 
+# The relocation for local_var should be resolved by the linker.
 # CHECK: Relocations [
+# CHECK: .rela.dyn {
+# CHECK-NEXT: R_AMDGPU_ABS64 common_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 extern_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 global_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 weak_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 weakref_alias_var 0x0
+# CHECK-NEXT: }
 # CHECK-NEXT: ]
Index: lld/trunk/ELF/Target.cpp
===================================================================
--- lld/trunk/ELF/Target.cpp
+++ lld/trunk/ELF/Target.cpp
@@ -166,7 +166,7 @@
 
 class AMDGPUTargetInfo final : public TargetInfo {
 public:
-  AMDGPUTargetInfo() {}
+  AMDGPUTargetInfo();
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
 };
@@ -1415,16 +1415,29 @@
   llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
 }
 
+AMDGPUTargetInfo::AMDGPUTargetInfo() { GotRel = R_AMDGPU_ABS64; }
+
 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                    uint64_t Val) const {
-  assert(Type == R_AMDGPU_REL32);
-  write32le(Loc, Val);
+  switch (Type) {
+  case R_AMDGPU_GOTPCREL:
+  case R_AMDGPU_REL32:
+    write32le(Loc, Val);
+    break;
+  default:
+    fatal("unrecognized reloc " + Twine(Type));
+  }
 }
 
 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
-  if (Type != R_AMDGPU_REL32)
-    error("do not know how to handle relocation");
-  return R_PC;
+  switch (Type) {
+  case R_AMDGPU_REL32:
+    return R_PC;
+  case R_AMDGPU_GOTPCREL:
+    return R_GOT_PC;
+  default:
+    fatal("do not know how to handle relocation " + Twine(Type));
+  }
 }
 
 ARMTargetInfo::ARMTargetInfo() {


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