[PATCH] D21956: AVX-512: Optimization for patterns with i1 scalar type
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 4 05:32:30 PDT 2016
igorb accepted this revision.
igorb added a comment.
This revision is now accepted and ready to land.
few minor comments,
LGTM
================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:15518
@@ -15508,3 +15517,3 @@
DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
- if (Op.getSimpleValueType() == MVT::i1)
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
+ if (Op.getSimpleValueType() == MVT::i1) {
+ SetCC = DAG.getNode(ISD::AssertZext, DL, MVT::i8, SetCC,
----------------
This is common sequence, may be it worth to create small help function.
================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:15551
@@ -15538,2 +15550,3 @@
}
+static SDValue getCondAfterTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
----------------
could you please add a few lines of comments
================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:26618
@@ -26590,3 +26617,3 @@
bool truncatedToBoolWithAnd = false;
// Skip (zext $x), (trunc $x), or (and $x, 1) node.
while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
----------------
could you please update commnets
Repository:
rL LLVM
http://reviews.llvm.org/D21956
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