[llvm] r274474 - [X86][AVX2] Merge unary permute matching behind the same V2.isUndef() condition. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 3 13:39:42 PDT 2016
Author: rksimon
Date: Sun Jul 3 15:39:42 2016
New Revision: 274474
URL: http://llvm.org/viewvc/llvm-project?rev=274474&view=rev
Log:
[X86][AVX2] Merge unary permute matching behind the same V2.isUndef() condition. NFCI.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274474&r1=274473&r2=274474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 3 15:39:42 2016
@@ -11216,11 +11216,11 @@ static SDValue lowerV4I64VectorShuffle(c
Mask, Subtarget, DAG))
return Broadcast;
- // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
- // use lower latency instructions that will operate on both 128-bit lanes.
- SmallVector<int, 2> RepeatedMask;
- if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
- if (V2.isUndef()) {
+ if (V2.isUndef()) {
+ // When the shuffle is mirrored between the 128-bit lanes of the unit, we
+ // can use lower latency instructions that will operate on both lanes.
+ SmallVector<int, 2> RepeatedMask;
+ if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
int PSHUFDMask[] = {-1, -1, -1, -1};
for (int i = 0; i < 2; ++i)
if (RepeatedMask[i] >= 0) {
@@ -11233,13 +11233,12 @@ static SDValue lowerV4I64VectorShuffle(c
DAG.getBitcast(MVT::v8i32, V1),
getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
}
- }
- // AVX2 provides a direct instruction for permuting a single input across
- // lanes.
- if (V2.isUndef())
+ // AVX2 provides a direct instruction for permuting a single input across
+ // lanes.
return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
+ }
// Try to use shift instructions.
if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask,
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