[llvm] r274468 - [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQ
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 3 11:27:38 PDT 2016
Author: rksimon
Date: Sun Jul 3 13:27:37 2016
New Revision: 274468
URL: http://llvm.org/viewvc/llvm-project?rev=274468&view=rev
Log:
[X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQ
Modified:
llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp
llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=274468&r1=274467&r2=274468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Sun Jul 3 13:27:37 2016
@@ -127,6 +127,11 @@ using namespace llvm;
CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
+#define CASE_VPERM(Inst, src) \
+ CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
+ CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
+ CASE_AVX_INS_COMMON(Inst, Y, src##i)
+
#define CASE_VSHUF(Inst, src) \
CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
@@ -826,26 +831,24 @@ bool llvm::EmitAnyX86InstComments(const
DestName = getRegName(MI->getOperand(0).getReg());
break;
- case X86::VPERMQYri:
- case X86::VPERMQZ256ri:
- case X86::VPERMQZ256rik:
- case X86::VPERMQZ256rikz:
- case X86::VPERMPDYri:
- case X86::VPERMPDZ256ri:
- case X86::VPERMPDZ256rik:
- case X86::VPERMPDZ256rikz:
+ CASE_VPERM(PERMPD, r)
+ Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
+ // FALL THROUGH.
+ CASE_VPERM(PERMPD, m)
+ if (MI->getOperand(NumOperands - 1).isImm())
+ DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
+ MI->getOperand(NumOperands - 1).getImm(),
+ ShuffleMask);
+ DestName = getRegName(MI->getOperand(0).getReg());
+ break;
+
+ CASE_VPERM(PERMQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
- case X86::VPERMQYmi:
- case X86::VPERMQZ256mi:
- case X86::VPERMQZ256mik:
- case X86::VPERMQZ256mikz:
- case X86::VPERMPDYmi:
- case X86::VPERMPDZ256mi:
- case X86::VPERMPDZ256mik:
- case X86::VPERMPDZ256mikz:
+ CASE_VPERM(PERMQ, m)
if (MI->getOperand(NumOperands - 1).isImm())
- DecodeVPERMMask(MI->getOperand(NumOperands - 1).getImm(),
+ DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp?rev=274468&r1=274467&r2=274468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp (original)
+++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp Sun Jul 3 13:27:37 2016
@@ -382,12 +382,14 @@ void DecodeVPPERMMask(ArrayRef<uint64_t>
}
}
- /// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
-/// No VT provided since it only works on 256-bit, 4 element vectors.
-void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
- for (unsigned i = 0; i != 4; ++i) {
- ShuffleMask.push_back((Imm >> (2 * i)) & 3);
- }
+/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
+void DecodeVPERMMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
+ assert((VT.is256BitVector() || VT.is512BitVector()) &&
+ (VT.getScalarSizeInBits() == 64) && "Unexpected vector value type");
+ unsigned NumElts = VT.getVectorNumElements();
+ for (unsigned l = 0; l != NumElts; l += 4)
+ for (unsigned i = 0; i != 4; ++i)
+ ShuffleMask.push_back(l + ((Imm >> (2 * i)) & 3));
}
void DecodeZeroExtendMask(MVT SrcScalarVT, MVT DstVT, SmallVectorImpl<int> &Mask) {
Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h?rev=274468&r1=274467&r2=274468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h (original)
+++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h Sun Jul 3 13:27:37 2016
@@ -105,8 +105,7 @@ void decodeVSHUF64x2FamilyMask(MVT VT, u
SmallVectorImpl<int> &ShuffleMask);
/// Decodes the shuffle masks for VPERMQ/VPERMPD.
-/// No VT provided since it only works on 256-bit, 4 element vectors.
-void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
+void DecodeVPERMMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
/// Decode a VPPERM mask from a raw array of constants such as from
/// BUILD_VECTOR.
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274468&r1=274467&r2=274468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 3 13:27:37 2016
@@ -4940,7 +4940,7 @@ static bool getTargetShuffleMask(SDNode
}
case X86ISD::VPERMI:
ImmN = N->getOperand(N->getNumOperands()-1);
- DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+ DecodeVPERMMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
IsUnary = true;
break;
case X86ISD::MOVSS:
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274468&r1=274467&r2=274468&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Sun Jul 3 13:27:37 2016
@@ -6352,9 +6352,9 @@ define <8 x double>@test_int_x86_avx512_
; CHECK-LABEL: test_int_x86_avx512_mask_perm_df_512:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpermpd $3, %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vpermpd $3, %zmm0, %zmm2 {%k1} {z}
-; CHECK-NEXT: vpermpd $3, %zmm0, %zmm0
+; CHECK-NEXT: vpermpd {{.*#+}} zmm1 = zmm0[3,0,0,0,7,4,4,4]
+; CHECK-NEXT: vpermpd {{.*#+}} zmm2 = zmm0[3,0,0,0,7,4,4,4]
+; CHECK-NEXT: vpermpd {{.*#+}} zmm0 = zmm0[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
@@ -6372,9 +6372,9 @@ define <8 x i64>@test_int_x86_avx512_mas
; CHECK-LABEL: test_int_x86_avx512_mask_perm_di_512:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpermq $3, %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vpermq $3, %zmm0, %zmm2 {%k1} {z}
-; CHECK-NEXT: vpermq $3, %zmm0, %zmm0
+; CHECK-NEXT: vpermq {{.*#+}} zmm1 = zmm0[3,0,0,0,7,4,4,4]
+; CHECK-NEXT: vpermq {{.*#+}} zmm2 = zmm0[3,0,0,0,7,4,4,4]
+; CHECK-NEXT: vpermq {{.*#+}} zmm0 = zmm0[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
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