[PATCH] D19917: AMDGPU/SI: Add amdgpu_kernel calling convention.

[Nikolay Haustov via llvm-commits]

This revision was automatically updated to reflect the committed changes.
nhaustov marked an inline comment as done.
Closed by commit rL274341: Resubmit r268719 - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2. (authored by nhaustov).

Changed prior to commit:
  http://reviews.llvm.org/D19917?vs=56267&id=62477#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D19917

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.h
  llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll

Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
@@ -12,4 +12,12 @@
   LDSSize(0),
   ABIArgOffset(0),
   ScratchSize(0),
-  IsKernel(true) {}
+  IsKernel(MF.getFunction()->getCallingConv() == llvm::CallingConv::AMDGPU_KERNEL ||
+           MF.getFunction()->getCallingConv() == llvm::CallingConv::SPIR_KERNEL)
+{
+}
+
+bool AMDGPUMachineFunction::isKernel() const
+{
+  return IsKernel;
+}
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.h
@@ -44,10 +44,7 @@
   /// Start of implicit kernel args
   unsigned ABIArgOffset;
 
-  bool isKernel() const {
-    // FIXME: Assume everything is a kernel until function calls are supported.
-    return true;
-  }
+  bool isKernel() const;
 
   unsigned ScratchSize;
   bool IsKernel;
Index: llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll
@@ -0,0 +1,61 @@
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo  | FileCheck --check-prefix=HSA %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
+
+; The SHT_NOTE section contains the output from the .hsa_code_object_*
+; directives.
+
+; ELF: Section {
+; ELF: Name: .text
+; ELF: Type: SHT_PROGBITS (0x1)
+; ELF: Flags [ (0x6)
+; ELF: SHF_ALLOC (0x2)
+; ELF: SHF_EXECINSTR (0x4)
+; ELF: }
+
+; ELF: SHT_NOTE
+; ELF: 0000: 04000000 08000000 01000000 414D4400
+; ELF: 0010: 02000000 00000000 04000000 1B000000
+
+; ELF: 0020: 03000000 414D4400 04000700 07000000
+; ELF: 0030: 00000000 00000000 414D4400 414D4447
+; ELF: 0040: 50550000
+
+; ELF: Symbol {
+; ELF: Name: simple
+; ELF: Size: 288
+; ELF: Type: Function (0x2)
+; ELF: }
+
+; HSA: .hsa_code_object_version 2,0
+; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
+; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
+
+; HSA: .text
+
+; HSA-NOT: .amdgpu_hsa_kernel simple
+; HSA: {{^}}simple:
+; HSA: .amd_kernel_code_t
+; HSA: enable_sgpr_private_segment_buffer = 1
+; HSA: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: .end_amd_kernel_code_t
+; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
+
+; Make sure we are setting the ATC bit:
+; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
+; On VI+ we also need to set MTYPE = 2
+; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
+; Make sure we generate flat store for HSA
+; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
+
+; HSA: .Lfunc_end0:
+; HSA: .size   simple, .Lfunc_end0-simple
+
+define void @simple(i32 addrspace(1)* %out) {
+entry:
+  store i32 0, i32 addrspace(1)* %out
+  ret void
+}


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