[llvm] r274216 - [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Thu Jun 30 02:13:56 2016
New Revision: 274216

URL: http://llvm.org/viewvc/llvm-project?rev=274216&view=rev
Log:
[SystemZ] Let z13 also support FeatureMiscellaneousExtensions.

This processor feature had been left out by mistake from the z13
ProcessorModel.

This time with updated test case. Thanks, Hans.

Reviewed by Ulrich Weigand.

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
    llvm/trunk/test/CodeGen/SystemZ/vec-extract-02.ll

Modified: llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td?rev=274216&r1=274215&r2=274216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td Thu Jun 30 02:13:56 2016
@@ -92,5 +92,6 @@ def : Processor<"z13", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1,
+                 FeatureMiscellaneousExtensions,
                  FeatureTransactionalExecution, FeatureProcessorAssist,
                  FeatureVector]>;

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-extract-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-extract-02.ll?rev=274216&r1=274215&r2=274216&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-extract-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-extract-02.ll Thu Jun 30 02:13:56 2016
@@ -6,7 +6,7 @@
 ; The index must be extended from i32 to i64.
 define i32 @f1(<4 x i32> *%ptr, i32 %index) {
 ; CHECK-LABEL: f1:
-; CHECK: risbg {{%r[0-5]}}, %r3, 30, 189, 2
+; CHECK: risbgn {{%r[0-5]}}, %r3, 30, 189, 2
 ; CHECK: l %r2,
 ; CHECK: br %r14
   %vec = load <4 x i32>, <4 x i32> *%ptr