[PATCH] D21774: [X86] Transform setcc + movzbl into xorl + setcc

[Michael Kuperstein via llvm-commits]

mkuper added a comment.

I played around with it a bit more, and it seems like doing this in DAGToDAG is too early.
This just doesn't play well with higher-level optimizations. In addition to the legalize-shift-64.ll case above, the DAGToDAG patch doesn't even fix the original case PR28146 was reduced from. There, the MOV32r0 gets hoisted up by MachineLICM, with the result being a similar setcc + mov 0 + movb pattern.

Ahmed, are you OK with keeping this a late (after SSA optimizations) pre-RA pass? Or do you prefer to try again with pseudos, like Dave proposed? Any other suggestions?

Dave, regarding performance: this patch (the machine IR pass) looks performance-neutral on SPEC2006. 
And, of course, it improves the performance of the workload PR28146 was reduced from by the expected amount. :-)


http://reviews.llvm.org/D21774