[llvm] r274194 - RegisterScavenging: Code cleanup; NFC
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 29 17:23:54 PDT 2016
Author: matze
Date: Wed Jun 29 19:23:54 2016
New Revision: 274194
URL: http://llvm.org/viewvc/llvm-project?rev=274194&view=rev
Log:
RegisterScavenging: Code cleanup; NFC
- Use range based for loops
- No need for some !Reg checks: isPhysicalRegister() reports false for
NoRegister anyway
- Do not repeat function name in documentation comment.
- Do not repeat documentation comment in implementation when we already
have one at the declaration.
- Factor some common subexpressions out.
- Change file comments to use doxygen syntax.
Modified:
llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=274194&r1=274193&r2=274194&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Wed Jun 29 19:23:54 2016
@@ -7,10 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
-// This file declares the machine register scavenger class. It can provide
-// information such as unused register at any point in a machine basic block.
-// It also provides a mechanism to make registers available by evicting them
-// to spill slots.
+/// \file
+/// This file declares the machine register scavenger class. It can provide
+/// information such as unused register at any point in a machine basic block.
+/// It also provides a mechanism to make registers available by evicting them
+/// to spill slots.
//
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=274194&r1=274193&r2=274194&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Wed Jun 29 19:23:54 2016
@@ -7,10 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the machine register scavenger. It can provide
-// information, such as unused registers, at any point in a machine basic block.
-// It also provides a mechanism to make registers available by evicting them to
-// spill slots.
+/// \file
+/// This file implements the machine register scavenger. It can provide
+/// information, such as unused registers, at any point in a machine basic
+/// block. It also provides a mechanism to make registers available by evicting
+/// them to spill slots.
//
//===----------------------------------------------------------------------===//
@@ -30,7 +31,6 @@ using namespace llvm;
#define DEBUG_TYPE "reg-scavenging"
-/// setUsed - Set the register units of this register as used.
void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
LaneBitmask UnitMask = (*RUI).second;
@@ -104,10 +104,8 @@ void RegScavenger::determineKillsAndDefs
// def-dead in this instruction.
KillRegUnits.reset();
DefRegUnits.reset();
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (MO.isRegMask()) {
-
TmpRegUnits.clear();
for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
@@ -117,14 +115,14 @@ void RegScavenger::determineKillsAndDefs
}
}
}
-
+
// Apply the mask.
KillRegUnits |= TmpRegUnits;
}
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
- if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
+ if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg))
continue;
if (MO.isUse()) {
@@ -191,12 +189,11 @@ void RegScavenger::forward() {
// Verify uses and defs.
#ifndef NDEBUG
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
- if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
+ if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg))
continue;
if (MO.isUse()) {
if (MO.isUndef())
@@ -258,33 +255,24 @@ bool RegScavenger::isRegUsed(unsigned Re
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
- for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
- I != E; ++I)
- if (!isRegUsed(*I)) {
- DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
+ for (unsigned Reg : *RC) {
+ if (!isRegUsed(Reg)) {
+ DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) <<
"\n");
- return *I;
+ return Reg;
}
+ }
return 0;
}
-/// getRegsAvailable - Return all available registers in the register class
-/// in Mask.
BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
BitVector Mask(TRI->getNumRegs());
- for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
- I != E; ++I)
- if (!isRegUsed(*I))
- Mask.set(*I);
+ for (unsigned Reg : *RC)
+ if (!isRegUsed(Reg))
+ Mask.set(Reg);
return Mask;
}
-/// findSurvivorReg - Return the candidate register that is unused for the
-/// longest after StartMII. UseMI is set to the instruction where the search
-/// stopped.
-///
-/// No more than InstrLimit instructions are inspected.
-///
unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
BitVector &Candidates,
unsigned InstrLimit,
@@ -306,8 +294,7 @@ unsigned RegScavenger::findSurvivorReg(M
bool isVirtKillInsn = false;
bool isVirtDefInsn = false;
// Remove any candidates touched by instruction.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (MO.isRegMask())
Candidates.clearBitsNotInMask(MO.getRegMask());
if (!MO.isReg() || MO.isUndef() || !MO.getReg())
@@ -342,8 +329,8 @@ unsigned RegScavenger::findSurvivorReg(M
}
// If we ran off the end, that's where we want to restore.
if (MI == ME) RestorePointMI = ME;
- assert (RestorePointMI != StartMI &&
- "No available scavenger restore location!");
+ assert(RestorePointMI != StartMI &&
+ "No available scavenger restore location!");
// We ran out of candidates, so stop the search.
UseMI = RestorePointMI;
@@ -363,13 +350,13 @@ static unsigned getFrameIndexOperandNum(
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
MachineBasicBlock::iterator I,
int SPAdj) {
+ MachineInstr &MI = *I;
+ const MachineFunction &MF = *MI.getParent()->getParent();
// Consider all allocatable registers in the register class initially
- BitVector Candidates =
- TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
+ BitVector Candidates = TRI->getAllocatableSet(MF, RC);
// Exclude all the registers being used by the instruction.
- for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = I->getOperand(i);
+ for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg());
@@ -394,8 +381,7 @@ unsigned RegScavenger::scavengeRegister(
// Find an available scavenging slot with size and alignment matching
// the requirements of the class RC.
- MachineFunction &MF = *I->getParent()->getParent();
- MachineFrameInfo &MFI = *MF.getFrameInfo();
+ const MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned NeedSize = RC->getSize();
unsigned NeedAlign = RC->getAlignment();
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