[llvm] r274141 - Revert r272251, it caused PR28348.

[Nico Weber via llvm-commits]

Author: nico
Date: Wed Jun 29 12:33:41 2016
New Revision: 274141

URL: http://llvm.org/viewvc/llvm-project?rev=274141&view=rev
Log:
Revert r272251, it caused PR28348.

Removed:
    llvm/trunk/test/CodeGen/Thumb/bic_imm.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=274141&r1=274140&r2=274141&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Jun 29 12:33:41 2016
@@ -2820,45 +2820,6 @@ void ARMDAGToDAGISel::Select(SDNode *N)
     if (tryV6T2BitfieldExtractOp(N, false))
       return;
 
-    // If an immediate is used in an AND node, it is possible that the immediate
-    // can be more optimally materialized when negated. If this is the case we
-    // can negate the immediate and use a BIC instead.
-    auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
-    if (N1C && N1C->hasOneUse() && Subtarget->isThumb()) {
-      uint32_t Imm = (uint32_t) N1C->getZExtValue();
-
-      // In Thumb2 mode, an AND can take a 12-bit immediate. If this
-      // immediate can be negated and fit in the immediate operand of
-      // a t2BIC, don't do any manual transform here as this can be
-      // handled by the generic ISel machinery.
-      bool PreferImmediateEncoding =
-          Subtarget->hasThumb2() && !is_t2_so_imm(Imm) && is_t2_so_imm_not(Imm);
-      if (!PreferImmediateEncoding &&
-          ConstantMaterializationCost(Imm) >
-              ConstantMaterializationCost(~Imm)) {
-        // The current immediate costs more to materialize than a negated
-        // immediate, so negate the immediate and use a BIC.
-        SDValue NewImm =
-            CurDAG->getConstant(~N1C->getZExtValue(), dl, MVT::i32);
-        CurDAG->RepositionNode(N->getIterator(), NewImm.getNode());
-
-        if (!Subtarget->hasThumb2()) {
-          SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
-                           N->getOperand(0), NewImm, getAL(CurDAG, dl),
-                           CurDAG->getRegister(0, MVT::i32)};
-          ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
-          return;
-        } else {
-          SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
-                           CurDAG->getRegister(0, MVT::i32),
-                           CurDAG->getRegister(0, MVT::i32)};
-          ReplaceNode(N,
-                      CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
-          return;
-        }
-      }
-    }
-
     // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
     // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
     // are entirely contributed by c2 and lower 16-bits are entirely contributed
@@ -2873,7 +2834,7 @@ void ARMDAGToDAGISel::Select(SDNode *N)
     if (!Opc)
       break;
     SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
-    N1C = dyn_cast<ConstantSDNode>(N1);
+    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
     if (!N1C)
       break;
     if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {

Removed: llvm/trunk/test/CodeGen/Thumb/bic_imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/bic_imm.ll?rev=274140&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/bic_imm.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/bic_imm.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m0 -verify-machineinstrs | FileCheck --check-prefix CHECK-T1 %s
-; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m3 -verify-machineinstrs | FileCheck --check-prefix CHECK-T2 %s
-
-; CHECK-T1-LABEL: @i
-; CHECK-T2-LABEL: @i
-; CHECK-T1: movs r1, #255
-; CHECK-T1: adds r1, #20
-; CHECK-T1: bics r0, r1
-; CHECK-T2: movw r1, #275
-; CHECK-T2: bics r0, r1
-define i32 @i(i32 %a) {
-entry:
-  %and = and i32 %a, -276
-  ret i32 %and
-}