[PATCH] D21802: Ensure all uses of permute instruction feed vector stores

[Nemanja Ivanovic via llvm-commits]

nemanjai added a comment.

I'm just curious how this happens since the swap instruction that defines the register for the store is emitted together with the actual store. How is there another user for a node that the back end added as part of DAG combine? I assume this is some sort of CSE that is running between the combine step and the swap removal step? If it is, might it also be advantageous to teach it not to eliminate expressions when one of them is a swap feeding a store?

I'm not suggesting this is necessarily the right thing to do, but one thing that will prevent `MachineCSE` from eliminating swaps is by adding `let hasSideEffects = 1` in the definition of `XXPERMDI`. That fixes this issue, but has the disadvantage of disabling CSE for other forms of the instruction.

In any case, disabling `MachineCSE` for swaps might be something we want to consider.


http://reviews.llvm.org/D21802