[PATCH] D21726: CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
Duncan P. N. Exon Smith via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 28 18:57:02 PDT 2016
dexonsmith updated this revision to Diff 62164.
dexonsmith added a comment.
- Spell NULL as nullptr in moved comment, and clean up the areCFlagsAccessedBetweenInstrs helper in AArch64InstrInfo.cpp (responding to Ahmed's feedback).
- Update off-by-default targets.
http://reviews.llvm.org/D21726
Files:
include/llvm/Target/TargetInstrInfo.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/CalcSpillWeights.cpp
lib/CodeGen/ExecutionDepsFix.cpp
lib/CodeGen/ExpandPostRAPseudos.cpp
lib/CodeGen/ImplicitNullChecks.cpp
lib/CodeGen/InlineSpiller.cpp
lib/CodeGen/LiveRangeEdit.cpp
lib/CodeGen/MachineCSE.cpp
lib/CodeGen/MachineLICM.cpp
lib/CodeGen/MachineScheduler.cpp
lib/CodeGen/MachineSink.cpp
lib/CodeGen/MachineVerifier.cpp
lib/CodeGen/PeepholeOptimizer.cpp
lib/CodeGen/PostRASchedulerList.cpp
lib/CodeGen/PrologEpilogInserter.cpp
lib/CodeGen/RegisterCoalescer.cpp
lib/CodeGen/ScheduleDAGInstrs.cpp
lib/CodeGen/StackSlotColoring.cpp
lib/CodeGen/TailDuplicator.cpp
lib/CodeGen/TargetInstrInfo.cpp
lib/CodeGen/TargetSchedule.cpp
lib/CodeGen/TwoAddressInstructionPass.cpp
lib/Target/AArch64/AArch64BranchRelaxation.cpp
lib/Target/AArch64/AArch64InstrInfo.cpp
lib/Target/AArch64/AArch64InstrInfo.h
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
lib/Target/AArch64/AArch64SchedCyclone.td
lib/Target/AArch64/AArch64Schedule.td
lib/Target/AArch64/AArch64StorePairSuppress.cpp
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
lib/Target/AMDGPU/R600ClauseMergePass.cpp
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
lib/Target/AMDGPU/R600ISelLowering.cpp
lib/Target/AMDGPU/R600InstrInfo.cpp
lib/Target/AMDGPU/R600InstrInfo.h
lib/Target/AMDGPU/R600MachineScheduler.cpp
lib/Target/AMDGPU/R600Packetizer.cpp
lib/Target/AMDGPU/SIFoldOperands.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstrInfo.h
lib/Target/AMDGPU/SIMachineScheduler.cpp
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIShrinkInstructions.cpp
lib/Target/ARM/ARMBaseInstrInfo.cpp
lib/Target/ARM/ARMBaseInstrInfo.h
lib/Target/ARM/ARMConstantIslandPass.cpp
lib/Target/ARM/ARMFrameLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMScheduleA9.td
lib/Target/ARM/ARMScheduleSwift.td
lib/Target/ARM/Thumb2SizeReduction.cpp
lib/Target/AVR/AVRInstrInfo.cpp
lib/Target/AVR/AVRInstrInfo.h
lib/Target/Hexagon/HexagonExpandCondsets.cpp
lib/Target/Hexagon/HexagonFrameLowering.cpp
lib/Target/Hexagon/HexagonHardwareLoops.cpp
lib/Target/Hexagon/HexagonInstrInfo.cpp
lib/Target/Hexagon/HexagonInstrInfo.h
lib/Target/Hexagon/HexagonSplitDouble.cpp
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
lib/Target/Lanai/LanaiInstrInfo.cpp
lib/Target/Lanai/LanaiInstrInfo.h
lib/Target/Mips/Mips16InstrInfo.cpp
lib/Target/Mips/Mips16InstrInfo.h
lib/Target/Mips/MipsSEInstrInfo.cpp
lib/Target/Mips/MipsSEInstrInfo.h
lib/Target/PowerPC/PPCBranchSelector.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrInfo.cpp
lib/Target/PowerPC/PPCInstrInfo.h
lib/Target/Sparc/SparcInstrInfo.cpp
lib/Target/Sparc/SparcInstrInfo.h
lib/Target/SystemZ/SystemZInstrInfo.cpp
lib/Target/SystemZ/SystemZInstrInfo.h
lib/Target/SystemZ/SystemZLongBranch.cpp
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
lib/Target/WebAssembly/WebAssemblyInstrInfo.h
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
lib/Target/X86/X86AsmPrinter.cpp
lib/Target/X86/X86FastISel.cpp
lib/Target/X86/X86FixupLEAs.cpp
lib/Target/X86/X86FrameLowering.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrInfo.cpp
lib/Target/X86/X86InstrInfo.h
lib/Target/X86/X86PadShortFunction.cpp
lib/Target/XCore/XCoreInstrInfo.cpp
lib/Target/XCore/XCoreInstrInfo.h
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