[PATCH] D21826: AArch64: Change modeling of zero cycle zeroing.

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added reviewers: mcrosier, t.p.northover.
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AArch64: Change modeling of zero cycle zeroing.

On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should
be used to zero a vector register. This was previously done at
instruction selection time, however the register coalescer sometimes
widened multiple vregs to the Q width because of that leading to extra
spills. This patch leaves the decision on how to zero a register to the
AsmPrinter phase where it doesn't affect register allocation anymore.

This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0.

This fixes http://llvm.org/PR27454, rdar://25866262

Repository:
  rL LLVM

http://reviews.llvm.org/D21826

Files:
  lib/Target/AArch64/AArch64AsmPrinter.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
  test/CodeGen/AArch64/fp-cond-sel.ll

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