[PATCH] D21774: [X86] Transform setcc + movzbl into xorl + setcc

[Michael Kuperstein via llvm-commits]

mkuper added a comment.

In http://reviews.llvm.org/D21774#469389, @ab wrote:

> +1 to David's comments about the weirdness around the dependencies.  I'm not sure how much of a problem that is in practice though, since that sounds like a pessimization that goes against register coalescing regardless of the specifics of this patch.
>  Speaking of which;  I looked a little closer at the ISel approach, and, with Matthias's and Quentin's help, I have a patch that looks like it works?  Can you give it a try: http://reviews.llvm.org/D21822


Ooh, this looks nice!
I actually tried to do it as a target-specific DAGCombine for zext and not in DAGToDAG, with something like:

  if (N0.getOpcode() == X86ISD::SETCC) {
    return DAG.getTargetInsertSubreg(
        X86::sub_8bit, dl, VT,
        SDValue(DAG.getMachineNode(X86::MOV32r0, dl, VT), 0), N0);
  }

But got stuck with the same kind of sub-optimal code, and couldn't see a way out.

I'll take a closer look at http://reviews.llvm.org/D21822, thanks!


http://reviews.llvm.org/D21774