[llvm] r273885 - [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 27 08:08:22 PDT 2016
Author: kparzysz
Date: Mon Jun 27 10:08:22 2016
New Revision: 273885
URL: http://llvm.org/viewvc/llvm-project?rev=273885&view=rev
Log:
[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
Added:
llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=273885&r1=273884&r2=273885&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Mon Jun 27 10:08:22 2016
@@ -104,6 +104,7 @@ public:
void SelectConstant(SDNode *N);
void SelectConstantFP(SDNode *N);
void SelectAdd(SDNode *N);
+ void SelectBitcast(SDNode *N);
void SelectBitOp(SDNode *N);
// XformMskToBitPosU5Imm - Returns the bit position which
@@ -1165,6 +1166,22 @@ void HexagonDAGToDAGISel::SelectFrameInd
}
+void HexagonDAGToDAGISel::SelectBitcast(SDNode *N) {
+ EVT SVT = N->getOperand(0).getValueType();
+ EVT DVT = N->getValueType(0);
+ if (!SVT.isVector() || !DVT.isVector() ||
+ SVT.getVectorElementType() == MVT::i1 ||
+ DVT.getVectorElementType() == MVT::i1 ||
+ SVT.getSizeInBits() != DVT.getSizeInBits()) {
+ SelectCode(N);
+ return;
+ }
+
+ CurDAG->ReplaceAllUsesOfValueWith(SDValue(N,0), N->getOperand(0));
+ CurDAG->RemoveDeadNode(N);
+}
+
+
void HexagonDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
N->setNodeId(-1);
@@ -1188,6 +1205,10 @@ void HexagonDAGToDAGISel::Select(SDNode
SelectAdd(N);
return;
+ case ISD::BITCAST:
+ SelectBitcast(N);
+ return;
+
case ISD::SHL:
SelectSHL(N);
return;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td?rev=273885&r1=273884&r2=273885&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td Mon Jun 27 10:08:22 2016
@@ -35,61 +35,12 @@ multiclass bitconvert_64<ValueType a, Va
(a DoubleRegs:$src)>;
}
-multiclass bitconvert_vec<ValueType a, ValueType b> {
- def : Pat <(b (bitconvert (a VectorRegs:$src))),
- (b VectorRegs:$src)>;
- def : Pat <(a (bitconvert (b VectorRegs:$src))),
- (a VectorRegs:$src)>;
-}
-
-multiclass bitconvert_dblvec<ValueType a, ValueType b> {
- def : Pat <(b (bitconvert (a VecDblRegs:$src))),
- (b VecDblRegs:$src)>;
- def : Pat <(a (bitconvert (b VecDblRegs:$src))),
- (a VecDblRegs:$src)>;
-}
-
-multiclass bitconvert_predvec<ValueType a, ValueType b> {
- def : Pat <(b (bitconvert (a VecPredRegs:$src))),
- (b VectorRegs:$src)>;
- def : Pat <(a (bitconvert (b VectorRegs:$src))),
- (a VecPredRegs:$src)>;
-}
-
-multiclass bitconvert_dblvec128B<ValueType a, ValueType b> {
- def : Pat <(b (bitconvert (a VecDblRegs128B:$src))),
- (b VecDblRegs128B:$src)>;
- def : Pat <(a (bitconvert (b VecDblRegs128B:$src))),
- (a VecDblRegs128B:$src)>;
-}
-
-// Bit convert vector types.
-defm : bitconvert_32<v4i8, i32>;
+// Bit convert vector types to integers.
+defm : bitconvert_32<v4i8, i32>;
defm : bitconvert_32<v2i16, i32>;
-defm : bitconvert_32<v2i16, v4i8>;
-
-defm : bitconvert_64<v8i8, i64>;
+defm : bitconvert_64<v8i8, i64>;
defm : bitconvert_64<v4i16, i64>;
defm : bitconvert_64<v2i32, i64>;
-defm : bitconvert_64<v8i8, v4i16>;
-defm : bitconvert_64<v8i8, v2i32>;
-defm : bitconvert_64<v4i16, v2i32>;
-
-defm : bitconvert_vec<v64i8, v16i32>;
-defm : bitconvert_vec<v8i64 , v16i32>;
-defm : bitconvert_vec<v32i16, v16i32>;
-
-defm : bitconvert_dblvec<v16i64, v128i8>;
-defm : bitconvert_dblvec<v32i32, v128i8>;
-defm : bitconvert_dblvec<v64i16, v128i8>;
-
-defm : bitconvert_dblvec128B<v64i32, v128i16>;
-defm : bitconvert_dblvec128B<v256i8, v128i16>;
-defm : bitconvert_dblvec128B<v32i64, v128i16>;
-
-defm : bitconvert_dblvec128B<v64i32, v256i8>;
-defm : bitconvert_dblvec128B<v32i64, v256i8>;
-defm : bitconvert_dblvec128B<v128i16, v256i8>;
// Vector shift support. Vector shifting in Hexagon is rather different
// from internal representation of LLVM.
Added: llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll?rev=273885&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/bitconvert-vector.ll Mon Jun 27 10:08:22 2016
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
+; is compiles without errors.
+; CHECK: valign
+; CHECK: vshuff
+
+target triple = "hexagon"
+
+declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
+declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0
+declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
+
+define void @fred() #1 {
+entry:
+ %t0 = bitcast <64 x i16> zeroinitializer to <32 x i32>
+ %t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2)
+ %t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2)
+ %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
+ store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128
+ store <32 x i32> %t3, <32 x i32>* undef, align 128
+ unreachable
+}
+
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
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