[llvm] r273873 - [ARM] Use member initializers in ARMSubtarget. NFCI
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 27 06:06:12 PDT 2016
Author: rovka
Date: Mon Jun 27 08:06:10 2016
New Revision: 273873
URL: http://llvm.org/viewvc/llvm-project?rev=273873&view=rev
Log:
[ARM] Use member initializers in ARMSubtarget. NFCI
Same as r273556, but with C++11 member initializers.
Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432).
Modified:
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=273873&r1=273872&r2=273873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jun 27 08:06:10 2016
@@ -89,34 +89,9 @@ ARMFrameLowering *ARMSubtarget::initiali
ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const ARMBaseTargetMachine &TM, bool IsLittle)
- : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
- ARMProcClass(None), ARMArch(ARMv4t), HasV4TOps(false), HasV5TOps(false),
- HasV5TEOps(false), HasV6Ops(false), HasV6MOps(false), HasV6KOps(false),
- HasV6T2Ops(false), HasV7Ops(false), HasV8Ops(false), HasV8_1aOps(false),
- HasV8_2aOps(false), HasV8MBaselineOps(false), HasV8MMainlineOps(false),
- HasVFPv2(false), HasVFPv3(false), HasVFPv4(false), HasFPARMv8(false),
- HasNEON(false), UseNEONForSinglePrecisionFP(false),
- UseMulOps(UseFusedMulOps), SlowFPVMLx(false), HasVMLxForwarding(false),
- SlowFPBrcc(false), InThumbMode(false), UseSoftFloat(false),
- HasThumb2(false), NoARM(false), ReserveR9(false), NoMovt(false),
- SupportsTailCall(false), HasFP16(false), HasFullFP16(false),
- HasD16(false), HasHardwareDivide(false), HasHardwareDivideInARM(false),
- HasT2ExtractPack(false), HasDataBarrier(false), HasV7Clrex(false),
- HasAcquireRelease(false), Pref32BitThumb(false),
- AvoidCPSRPartialUpdate(false), AvoidMOVsShifterOperand(false),
- HasRetAddrStack(false), HasMPExtension(false), HasVirtualization(false),
- FPOnlySP(false), HasPerfMon(false), HasTrustZone(false),
- Has8MSecExt(false), HasCrypto(false), HasCRC(false), HasRAS(false),
- HasZeroCycleZeroing(false), IsProfitableToUnpredicate(false),
- HasSlowVGETLNi32(false), HasSlowVDUP32(false), PreferVMOVSR(false),
- PreferISHST(false), UseNEONForFPMovs(false), CheckVLDnAlign(false),
- NonpipelinedVFP(false), StrictAlign(false), RestrictIT(false),
- HasDSP(false), UseNaClTrap(false), GenLongCalls(false),
- UnsafeFPMath(false), UseSjLjEH(false), stackAlignment(4), CPUString(CPU),
- MaxInterleaveFactor(1), LdStMultipleTiming(SingleIssue),
- PreISelOperandLatencyAdjustment(2), IsLittle(IsLittle), TargetTriple(TT),
- Options(TM.Options), TM(TM),
- FrameLowering(initializeFrameLowering(CPU, FS)),
+ : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
+ CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
+ TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
// At this point initializeSubtargetDependencies has been called so
// we can query directly.
InstrInfo(isThumb1Only()
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=273873&r1=273872&r2=273873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Jun 27 08:06:10 2016
@@ -73,232 +73,232 @@ public:
protected:
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
- ARMProcFamilyEnum ARMProcFamily;
+ ARMProcFamilyEnum ARMProcFamily = Others;
/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
- ARMProcClassEnum ARMProcClass;
+ ARMProcClassEnum ARMProcClass = None;
/// ARMArch - ARM architecture
- ARMArchEnum ARMArch;
+ ARMArchEnum ARMArch = ARMv4t;
/// HasV4TOps, HasV5TOps, HasV5TEOps,
/// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
/// Specify whether target support specific ARM ISA variants.
- bool HasV4TOps;
- bool HasV5TOps;
- bool HasV5TEOps;
- bool HasV6Ops;
- bool HasV6MOps;
- bool HasV6KOps;
- bool HasV6T2Ops;
- bool HasV7Ops;
- bool HasV8Ops;
- bool HasV8_1aOps;
- bool HasV8_2aOps;
- bool HasV8MBaselineOps;
- bool HasV8MMainlineOps;
+ bool HasV4TOps = false;
+ bool HasV5TOps = false;
+ bool HasV5TEOps = false;
+ bool HasV6Ops = false;
+ bool HasV6MOps = false;
+ bool HasV6KOps = false;
+ bool HasV6T2Ops = false;
+ bool HasV7Ops = false;
+ bool HasV8Ops = false;
+ bool HasV8_1aOps = false;
+ bool HasV8_2aOps = false;
+ bool HasV8MBaselineOps = false;
+ bool HasV8MMainlineOps = false;
/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
/// floating point ISAs are supported.
- bool HasVFPv2;
- bool HasVFPv3;
- bool HasVFPv4;
- bool HasFPARMv8;
- bool HasNEON;
+ bool HasVFPv2 = false;
+ bool HasVFPv3 = false;
+ bool HasVFPv4 = false;
+ bool HasFPARMv8 = false;
+ bool HasNEON = false;
/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
/// specified. Use the method useNEONForSinglePrecisionFP() to
/// determine if NEON should actually be used.
- bool UseNEONForSinglePrecisionFP;
+ bool UseNEONForSinglePrecisionFP = false;
/// UseMulOps - True if non-microcoded fused integer multiply-add and
/// multiply-subtract instructions should be used.
- bool UseMulOps;
+ bool UseMulOps = false;
/// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
/// whether the FP VML[AS] instructions are slow (if so, don't use them).
- bool SlowFPVMLx;
+ bool SlowFPVMLx = false;
/// HasVMLxForwarding - If true, NEON has special multiplier accumulator
/// forwarding to allow mul + mla being issued back to back.
- bool HasVMLxForwarding;
+ bool HasVMLxForwarding = false;
/// SlowFPBrcc - True if floating point compare + branch is slow.
- bool SlowFPBrcc;
+ bool SlowFPBrcc = false;
/// InThumbMode - True if compiling for Thumb, false for ARM.
- bool InThumbMode;
+ bool InThumbMode = false;
/// UseSoftFloat - True if we're using software floating point features.
- bool UseSoftFloat;
+ bool UseSoftFloat = false;
/// HasThumb2 - True if Thumb2 instructions are supported.
- bool HasThumb2;
+ bool HasThumb2 = false;
/// NoARM - True if subtarget does not support ARM mode execution.
- bool NoARM;
+ bool NoARM = false;
/// ReserveR9 - True if R9 is not available as a general purpose register.
- bool ReserveR9;
+ bool ReserveR9 = false;
/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
/// 32-bit imms (including global addresses).
- bool NoMovt;
+ bool NoMovt = false;
/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
/// must be able to synthesize call stubs for interworking between ARM and
/// Thumb.
- bool SupportsTailCall;
+ bool SupportsTailCall = false;
/// HasFP16 - True if subtarget supports half-precision FP conversions
- bool HasFP16;
+ bool HasFP16 = false;
/// HasFullFP16 - True if subtarget supports half-precision FP operations
- bool HasFullFP16;
+ bool HasFullFP16 = false;
/// HasD16 - True if subtarget is limited to 16 double precision
/// FP registers for VFPv3.
- bool HasD16;
+ bool HasD16 = false;
/// HasHardwareDivide - True if subtarget supports [su]div
- bool HasHardwareDivide;
+ bool HasHardwareDivide = false;
/// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
- bool HasHardwareDivideInARM;
+ bool HasHardwareDivideInARM = false;
/// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
/// instructions.
- bool HasT2ExtractPack;
+ bool HasT2ExtractPack = false;
/// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
/// instructions.
- bool HasDataBarrier;
+ bool HasDataBarrier = false;
/// HasV7Clrex - True if the subtarget supports CLREX instructions
- bool HasV7Clrex;
+ bool HasV7Clrex = false;
/// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
/// instructions
- bool HasAcquireRelease;
+ bool HasAcquireRelease = false;
/// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
/// over 16-bit ones.
- bool Pref32BitThumb;
+ bool Pref32BitThumb = false;
/// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
/// that partially update CPSR and add false dependency on the previous
/// CPSR setting instruction.
- bool AvoidCPSRPartialUpdate;
+ bool AvoidCPSRPartialUpdate = false;
/// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
/// movs with shifter operand (i.e. asr, lsl, lsr).
- bool AvoidMOVsShifterOperand;
+ bool AvoidMOVsShifterOperand = false;
/// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
/// avoid issue "normal" call instructions to callees which do not return.
- bool HasRetAddrStack;
+ bool HasRetAddrStack = false;
/// HasMPExtension - True if the subtarget supports Multiprocessing
/// extension (ARMv7 only).
- bool HasMPExtension;
+ bool HasMPExtension = false;
/// HasVirtualization - True if the subtarget supports the Virtualization
/// extension.
- bool HasVirtualization;
+ bool HasVirtualization = false;
/// FPOnlySP - If true, the floating point unit only supports single
/// precision.
- bool FPOnlySP;
+ bool FPOnlySP = false;
/// If true, the processor supports the Performance Monitor Extensions. These
/// include a generic cycle-counter as well as more fine-grained (often
/// implementation-specific) events.
- bool HasPerfMon;
+ bool HasPerfMon = false;
/// HasTrustZone - if true, processor supports TrustZone security extensions
- bool HasTrustZone;
+ bool HasTrustZone = false;
/// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
- bool Has8MSecExt;
+ bool Has8MSecExt = false;
/// HasCrypto - if true, processor supports Cryptography extensions
- bool HasCrypto;
+ bool HasCrypto = false;
/// HasCRC - if true, processor supports CRC instructions
- bool HasCRC;
+ bool HasCRC = false;
/// HasRAS - if true, the processor supports RAS extensions
- bool HasRAS;
+ bool HasRAS = false;
/// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
/// particularly effective at zeroing a VFP register.
- bool HasZeroCycleZeroing;
+ bool HasZeroCycleZeroing = false;
/// If true, if conversion may decide to leave some instructions unpredicated.
- bool IsProfitableToUnpredicate;
+ bool IsProfitableToUnpredicate = false;
/// If true, VMOV will be favored over VGETLNi32.
- bool HasSlowVGETLNi32;
+ bool HasSlowVGETLNi32 = false;
/// If true, VMOV will be favored over VDUP.
- bool HasSlowVDUP32;
+ bool HasSlowVDUP32 = false;
/// If true, VMOVSR will be favored over VMOVDRR.
- bool PreferVMOVSR;
+ bool PreferVMOVSR = false;
/// If true, ISHST barriers will be used for Release semantics.
- bool PreferISHST;
+ bool PreferISHST = false;
/// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
- bool UseNEONForFPMovs;
+ bool UseNEONForFPMovs = false;
/// If true, VLDn instructions take an extra cycle for unaligned accesses.
- bool CheckVLDnAlign;
+ bool CheckVLDnAlign = false;
/// If true, VFP instructions are not pipelined.
- bool NonpipelinedVFP;
+ bool NonpipelinedVFP = false;
/// StrictAlign - If true, the subtarget disallows unaligned memory
/// accesses for some types. For details, see
/// ARMTargetLowering::allowsMisalignedMemoryAccesses().
- bool StrictAlign;
+ bool StrictAlign = false;
/// RestrictIT - If true, the subtarget disallows generation of deprecated IT
/// blocks to conform to ARMv8 rule.
- bool RestrictIT;
+ bool RestrictIT = false;
/// HasDSP - If true, the subtarget supports the DSP (saturating arith
/// and such) instructions.
- bool HasDSP;
+ bool HasDSP = false;
/// NaCl TRAP instruction is generated instead of the regular TRAP.
- bool UseNaClTrap;
+ bool UseNaClTrap = false;
/// Generate calls via indirect call instructions.
- bool GenLongCalls;
+ bool GenLongCalls = false;
/// Target machine allowed unsafe FP math (such as use of NEON fp)
- bool UnsafeFPMath;
+ bool UnsafeFPMath = false;
/// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
- bool UseSjLjEH;
+ bool UseSjLjEH = false;
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
- unsigned stackAlignment;
+ unsigned stackAlignment = 4;
/// CPUString - String name of used CPU.
std::string CPUString;
- unsigned MaxInterleaveFactor;
+ unsigned MaxInterleaveFactor = 1;
/// What kind of timing do load multiple/store multiple have (double issue,
/// single issue etc).
- ARMLdStMultipleTiming LdStMultipleTiming;
+ ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
/// The adjustment that we need to apply to get the operand latency from the
/// operand cycle returned by the itinerary data for pre-ISel operands.
- int PreISelOperandLatencyAdjustment;
+ int PreISelOperandLatencyAdjustment = 2;
/// IsLittle - The target is Little Endian
bool IsLittle;
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