[PATCH] D21726: CodeGen: Use MachineInstr& in TargetInstrInfo, NFC

[Duncan P. N. Exon Smith via llvm-commits]

dexonsmith created this revision.
dexonsmith added reviewers: hfinkel, jfb, t.p.northover, bogner, kparzysz, tstellarAMD.
dexonsmith added a subscriber: llvm-commits.
Herald added subscribers: nemanjai, dsanders, jyknight, dschuff, arsenm, jfb, qcolombet, MatzeB, aemerson.

This is mostly a mechanical change to make TargetInstrInfo API take
MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator)
when the argument is expected to be a valid MachineInstr.  This is a
general API improvement.

Although it would be possible to do this one function at a time, that
would demand a quadratic amount of churn since many of these functions
call each other.  Instead I've done everything as a block and just
updated what was necessary.

This is mostly mechanical fixes: adding and removing `*` and `&`
operators.  The only non-mechanical change is to split
ARMBaseInstrInfo::getOperandLatencyImpl out from
ARMBaseInstrInfo::getOperandLatency.  Previously, the latter took a
`MachineInstr*` which it updated to the instruction bundle leader; now,
the latter calls the former either with the same `MachineInstr&` or the
bundle leader.

As a side effect, this removes a bunch of MachineInstr* to 
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

Since this is such a monolithic change (and annoying to revert), I'd
appreciate if a couple of others could confirm that the API changes in
TargetInstrInfo.h are reasonable before I push this.

http://reviews.llvm.org/D21726

Files:
  include/llvm/Target/TargetInstrInfo.h
  lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  lib/CodeGen/CalcSpillWeights.cpp
  lib/CodeGen/ExecutionDepsFix.cpp
  lib/CodeGen/ExpandPostRAPseudos.cpp
  lib/CodeGen/ImplicitNullChecks.cpp
  lib/CodeGen/InlineSpiller.cpp
  lib/CodeGen/LiveRangeEdit.cpp
  lib/CodeGen/MachineCSE.cpp
  lib/CodeGen/MachineLICM.cpp
  lib/CodeGen/MachineScheduler.cpp
  lib/CodeGen/MachineSink.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/PeepholeOptimizer.cpp
  lib/CodeGen/PostRASchedulerList.cpp
  lib/CodeGen/PrologEpilogInserter.cpp
  lib/CodeGen/RegisterCoalescer.cpp
  lib/CodeGen/ScheduleDAGInstrs.cpp
  lib/CodeGen/StackSlotColoring.cpp
  lib/CodeGen/TailDuplicator.cpp
  lib/CodeGen/TargetInstrInfo.cpp
  lib/CodeGen/TargetSchedule.cpp
  lib/CodeGen/TwoAddressInstructionPass.cpp
  lib/Target/AArch64/AArch64BranchRelaxation.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.h
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  lib/Target/AArch64/AArch64SchedCyclone.td
  lib/Target/AArch64/AArch64Schedule.td
  lib/Target/AArch64/AArch64StorePairSuppress.cpp
  lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  lib/Target/AMDGPU/R600ClauseMergePass.cpp
  lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
  lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
  lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
  lib/Target/AMDGPU/R600ISelLowering.cpp
  lib/Target/AMDGPU/R600InstrInfo.cpp
  lib/Target/AMDGPU/R600InstrInfo.h
  lib/Target/AMDGPU/R600MachineScheduler.cpp
  lib/Target/AMDGPU/R600Packetizer.cpp
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIMachineScheduler.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  lib/Target/ARM/ARMConstantIslandPass.cpp
  lib/Target/ARM/ARMFrameLowering.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMScheduleA9.td
  lib/Target/ARM/ARMScheduleSwift.td
  lib/Target/ARM/Thumb2SizeReduction.cpp
  lib/Target/Hexagon/HexagonExpandCondsets.cpp
  lib/Target/Hexagon/HexagonFrameLowering.cpp
  lib/Target/Hexagon/HexagonHardwareLoops.cpp
  lib/Target/Hexagon/HexagonInstrInfo.cpp
  lib/Target/Hexagon/HexagonInstrInfo.h
  lib/Target/Hexagon/HexagonSplitDouble.cpp
  lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  lib/Target/Mips/Mips16InstrInfo.cpp
  lib/Target/Mips/Mips16InstrInfo.h
  lib/Target/Mips/MipsSEInstrInfo.cpp
  lib/Target/Mips/MipsSEInstrInfo.h
  lib/Target/PowerPC/PPCBranchSelector.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrInfo.cpp
  lib/Target/PowerPC/PPCInstrInfo.h
  lib/Target/Sparc/SparcInstrInfo.cpp
  lib/Target/Sparc/SparcInstrInfo.h
  lib/Target/SystemZ/SystemZInstrInfo.cpp
  lib/Target/SystemZ/SystemZInstrInfo.h
  lib/Target/SystemZ/SystemZLongBranch.cpp
  lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
  lib/Target/WebAssembly/WebAssemblyInstrInfo.h
  lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  lib/Target/X86/X86AsmPrinter.cpp
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86FixupLEAs.cpp
  lib/Target/X86/X86FrameLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86InstrInfo.h
  lib/Target/X86/X86PadShortFunction.cpp
  lib/Target/XCore/XCoreInstrInfo.cpp
  lib/Target/XCore/XCoreInstrInfo.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D21726.61889.patch
Type: text/x-patch
Size: 618776 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160625/5adeda6a/attachment-0001.bin>