[PATCH] D21633: AMDGPU/R600: Fix GlobalValue regressions.

[Jan Vesely via llvm-commits]

jvesely updated this revision to Diff 61779.
jvesely added a comment.

change tests to output object format to test fixups

something like this might work. It detects crashes (and both bugs fixed in this patch) but not much else.
I was unsure about /dev/null, but it looks like the test has used it for some time. We can switch to %t0 if need be


Repository:
  rL LLVM

http://reviews.llvm.org/D21633

Files:
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
  lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
  test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll

Index: test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
===================================================================
--- test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
+++ test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mcpu=SI -o /dev/null %s
-; RUN: llc -march=amdgcn -mcpu=tonga -o /dev/null %s
-; RUN: llc -march=r600 -mcpu=cypress -o /dev/null %s
+; RUN: llc -march=amdgcn -mcpu=SI -filetype=obj -o /dev/null %s
+; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj -o /dev/null %s
+; RUN: llc -march=r600 -mcpu=cypress -filetype=obj -o /dev/null %s
 
 @extern_const_addrspace = external unnamed_addr addrspace(2) constant [5 x i32], align 4
 
Index: lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -163,7 +163,6 @@
   }
 
   if (MO.isExpr()) {
-    const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
     // We put rodata at the end of code section, then map the entire
     // code secetion as vtx buf. Thus the section relative address is the
     // correct one.
@@ -171,7 +170,7 @@
     // We can't easily get the order of the current one, so compare against
     // the first one and adjust offset.
     const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
-    Fixups.push_back(MCFixup::create(offset, Expr, FK_SecRel_4, MI.getLoc()));
+    Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
     return 0;
   }
 
Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -49,6 +49,8 @@
   default: break;
   case FK_PCRel_4:
     return ELF::R_AMDGPU_REL32;
+  case FK_SecRel_4:
+    return ELF::R_AMDGPU_NONE;;
   }
 
   llvm_unreachable("unhandled relocation type");


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