[llvm] r273658 - Revert "Revert "[misched] Extend scheduler to handle unsupported features""
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 24 01:43:28 PDT 2016
Author: sdardis
Date: Fri Jun 24 03:43:27 2016
New Revision: 273658
URL: http://llvm.org/viewvc/llvm-project?rev=273658&view=rev
Log:
Revert "Revert "[misched] Extend scheduler to handle unsupported features""
This reverts commit r273565.
This was an over-eager revert.
Modified:
llvm/trunk/include/llvm/Target/TargetSchedule.td
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
llvm/trunk/utils/TableGen/CodeGenSchedule.h
Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=273658&r1=273657&r2=273658&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td Fri Jun 24 03:43:27 2016
@@ -55,6 +55,8 @@ include "llvm/Target/TargetItinerary.td"
class Instruction; // Forward def
+class Predicate; // Forward def
+
// DAG operator that interprets the DAG args as Instruction defs.
def instrs;
@@ -97,6 +99,20 @@ class SchedMachineModel {
// resulting from changes to the instruction definitions.
bit CompleteModel = 1;
+ // A processor may only implement part of published ISA, due to either new ISA
+ // extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
+ // (ARM/MIPS/PowerPC/SPARC soft float cores).
+ //
+ // For a processor which doesn't support some feature(s), the schedule model
+ // can use:
+ //
+ // let<Predicate> UnsupportedFeatures = [HaveA,..,HaveY];
+ //
+ // to skip the checks for scheduling information when building LLVM for
+ // instructions which have any of the listed predicates in their Predicates
+ // field.
+ list<Predicate> UnsupportedFeatures = [];
+
bit NoModel = 0; // Special tag to indicate missing machine model.
}
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=273658&r1=273657&r2=273658&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Fri Jun 24 03:43:27 2016
@@ -120,6 +120,10 @@ CodeGenSchedModels::CodeGenSchedModels(R
// (For per-operand resources mapped to itinerary classes).
collectProcItinRW();
+ // Find UnsupportedFeatures records for each processor.
+ // (For per-operand resources mapped to itinerary classes).
+ collectProcUnsupportedFeatures();
+
// Infer new SchedClasses from SchedVariant.
inferSchedClasses();
@@ -829,6 +833,15 @@ void CodeGenSchedModels::collectProcItin
}
}
+// Gather the unsupported features for processor models.
+void CodeGenSchedModels::collectProcUnsupportedFeatures() {
+ for (CodeGenProcModel &ProcModel : ProcModels) {
+ for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) {
+ ProcModel.UnsupportedFeaturesDefs.push_back(Pred);
+ }
+ }
+}
+
/// Infer new classes from existing classes. In the process, this may create new
/// SchedWrites from sequences of existing SchedWrites.
void CodeGenSchedModels::inferSchedClasses() {
@@ -1540,6 +1553,8 @@ void CodeGenSchedModels::checkCompletene
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
if (Inst->hasNoSchedulingInfo)
continue;
+ if (ProcModel.isUnsupported(*Inst))
+ continue;
unsigned SCIdx = getSchedClassIdx(*Inst);
if (!SCIdx) {
if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
@@ -1575,7 +1590,10 @@ void CodeGenSchedModels::checkCompletene
<< "- Consider setting 'CompleteModel = 0' while developing new models.\n"
<< "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
<< "- Instructions should usually have Sched<[...]> as a superclass, "
- "you may temporarily use an empty list.\n\n";
+ "you may temporarily use an empty list.\n"
+ << "- Instructions related to unsupported features can be excluded with "
+ "list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
+ "processor model.\n\n";
PrintFatalError("Incomplete schedule model");
}
}
@@ -1756,6 +1774,16 @@ unsigned CodeGenProcModel::getProcResour
return 1 + (PRPos - ProcResourceDefs.begin());
}
+bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
+ for (const Record *TheDef : UnsupportedFeaturesDefs) {
+ for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
+ if (TheDef->getName() == PredDef->getName())
+ return true;
+ }
+ }
+ return false;
+}
+
#ifndef NDEBUG
void CodeGenProcModel::dump() const {
dbgs() << Index << ": " << ModelName << " "
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.h?rev=273658&r1=273657&r2=273658&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.h Fri Jun 24 03:43:27 2016
@@ -189,6 +189,10 @@ struct CodeGenProcModel {
// This list is empty if no ItinRW refers to this Processor.
RecVec ItinRWDefs;
+ // List of unsupported feature.
+ // This list is empty if the Processor has no UnsupportedFeatures.
+ RecVec UnsupportedFeaturesDefs;
+
// All read/write resources associated with this processor.
RecVec WriteResDefs;
RecVec ReadAdvanceDefs;
@@ -211,6 +215,8 @@ struct CodeGenProcModel {
unsigned getProcResourceIdx(Record *PRDef) const;
+ bool isUnsupported(const CodeGenInstruction &Inst) const;
+
#ifndef NDEBUG
void dump() const;
#endif
@@ -402,6 +408,8 @@ private:
void collectProcItinRW();
+ void collectProcUnsupportedFeatures();
+
void inferSchedClasses();
void checkCompleteness();
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