[PATCH] D21671: AMDGPU: Remove disable-irstructurizer subtarget feature
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 23 19:01:08 PDT 2016
arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm.
The only real reason to use it is for testing, so replace
it with a command line option instead of a potentially function
dependent feature.
http://reviews.llvm.org/D21671
Files:
lib/Target/AMDGPU/AMDGPU.td
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
lib/Target/AMDGPU/AMDGPUSubtarget.h
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
test/CodeGen/AMDGPU/predicates.ll
test/CodeGen/AMDGPU/structurize.ll
Index: test/CodeGen/AMDGPU/structurize.ll
===================================================================
--- test/CodeGen/AMDGPU/structurize.ll
+++ test/CodeGen/AMDGPU/structurize.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood -mattr=disable-irstructurizer | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood -r600-ir-structurize=0 | FileCheck %s
; Test case for a crash in the AMDILCFGStructurizer from a CFG like this:
;
; entry
Index: test/CodeGen/AMDGPU/predicates.ll
===================================================================
--- test/CodeGen/AMDGPU/predicates.ll
+++ test/CodeGen/AMDGPU/predicates.ll
@@ -1,4 +1,4 @@
-; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -mattr=disable-irstructurizer -mcpu=redwood < %s | FileCheck %s
+; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s
; These tests make sure the compiler is optimizing branches using predicates
; when it is legal to do so.
Index: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -40,6 +40,11 @@
using namespace llvm;
+static cl::opt<bool> EnableR600StructurizeCFG(
+ "r600-ir-structurize",
+ cl::desc("Use StructurizeCFG IR pass"),
+ cl::init(true));
+
extern "C" void LLVMInitializeAMDGPUTarget() {
// Register the target
RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
@@ -326,8 +331,8 @@
bool R600PassConfig::addPreISel() {
AMDGPUPassConfig::addPreISel();
- const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
- if (ST.IsIRStructurizerEnabled())
+
+ if (EnableR600StructurizeCFG)
addPass(createStructurizeCFGPass());
addPass(createR600TextureIntrinsicsReplacer());
return false;
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -80,7 +80,6 @@
// Used as options.
bool EnableVGPRSpilling;
- bool EnableIRStructurizer;
bool EnablePromoteAlloca;
bool EnableIfCvt;
bool EnableLoadStoreOpt;
@@ -218,10 +217,6 @@
return CaymanISA;
}
- bool IsIRStructurizerEnabled() const {
- return EnableIRStructurizer;
- }
-
bool isPromoteAllocaEnabled() const {
return EnablePromoteAlloca;
}
Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -103,7 +103,6 @@
DebuggerReserveRegs(false),
EnableVGPRSpilling(false),
- EnableIRStructurizer(true),
EnablePromoteAlloca(false),
EnableIfCvt(true),
EnableLoadStoreOpt(false),
Index: lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- lib/Target/AMDGPU/AMDGPU.td
+++ lib/Target/AMDGPU/AMDGPU.td
@@ -216,12 +216,6 @@
"Dump MachineInstrs in the CodeEmitter"
>;
-def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
- "EnableIRStructurizer",
- "false",
- "Disable IR Structurizer"
->;
-
def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
"EnablePromoteAlloca",
"true",
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