[llvm] r273549 - [mips] Fix dext/dins definitions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 23 02:06:21 PDT 2016
Author: sdardis
Date: Thu Jun 23 04:06:20 2016
New Revision: 273549
URL: http://llvm.org/viewvc/llvm-project?rev=273549&view=rev
Log:
[mips] Fix dext/dins definitions
dext and dins, along with their 'm' and 'u' variants are defined in mips64r2,
not mips64.
Reviewers: dsanders, vkalintiris
Differential Review: http://reviews.llvm.org/D21608
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=273549&r1=273548&r2=273549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Jun 23 04:06:20 2016
@@ -308,17 +308,19 @@ let AdditionalPredicates = [NotInMicroMi
// The 'pos + size' constraints are enforced by the code that lowers into
// MipsISD::Ext.
def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
- immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>;
+ immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>,
+ ISA_MIPS64R2;
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
- immZExt5Plus33, MipsExt>, EXT_FM<1>;
+ immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2;
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
- immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>;
+ immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
+ ISA_MIPS64R2;
def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>,
- EXT_FM<7>;
+ EXT_FM<7>, ISA_MIPS64R2;
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
- EXT_FM<6>;
+ EXT_FM<6>, ISA_MIPS64R2;
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
- EXT_FM<5>;
+ EXT_FM<5>, ISA_MIPS64R2;
}
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
Modified: llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s?rev=273549&r1=273548&r2=273549&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s Thu Jun 23 04:06:20 2016
@@ -6,6 +6,12 @@
.set noat
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dext $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dextm $1, $2, 21, 43 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dextu $1, $2, 33, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dins $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dinsm $1, $2, 21, 43 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dinsu $1, $2, 33, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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