[llvm] r273542 - [X86] Add assert to ensure only 128-bit vector types are used. 256 or 512-bit would require lane handling which is missing.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Jun 23 02:37:26 2016
New Revision: 273542

URL: http://llvm.org/viewvc/llvm-project?rev=273542&view=rev
Log:
[X86] Add assert to ensure only 128-bit vector types are used. 256 or 512-bit would require lane handling which is missing.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=273542&r1=273541&r2=273542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 23 02:37:26 2016
@@ -4684,6 +4684,7 @@ static SDValue getOnesVector(EVT VT, con
 /// Returns a vector_shuffle node for an unpackl operation.
 static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
                           SDValue V1, SDValue V2) {
+  assert(VT.is128BitVector() && "Expected a 128-bit vector type");
   unsigned NumElems = VT.getVectorNumElements();
   SmallVector<int, 8> Mask(NumElems);
   for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
@@ -4696,6 +4697,7 @@ static SDValue getUnpackl(SelectionDAG &
 /// Returns a vector_shuffle node for an unpackh operation.
 static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
                           SDValue V1, SDValue V2) {
+  assert(VT.is128BitVector() && "Expected a 128-bit vector type");
   unsigned NumElems = VT.getVectorNumElements();
   SmallVector<int, 8> Mask(NumElems);
   for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {