[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Renato Golin via llvm-commits]

rengolin added a comment.

Hi Evandro,

Unless Exynos chips can't handle indexed lanes at all, this looks like a case for the cost model, not CPU flags.

cheers,
--renato


http://reviews.llvm.org/D21571