[PATCH] D21560: Relax the clearance calculating for breaking partial register dependency.

[Sanjay Patel via llvm-commits]

spatel added a comment.

Since even the code comments acknowledge that this is a repeated magic number, please give it a name. Even better would be to make it a cl::opt, so we can run experiments more easily.

FWIW, I don't see any measurable perf difference for the example test case (compiled with -O2) running on Haswell.

Is there already a regression test to show that we're not adding instructions if we're in MinSize mode?


http://reviews.llvm.org/D21560