[llvm] r273432 - [Hexagon] Handle expansion of cmpxchg

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jun 22 11:07:10 2016
New Revision: 273432

URL: http://llvm.org/viewvc/llvm-project?rev=273432&view=rev
Log:
[Hexagon] Handle expansion of cmpxchg

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
    llvm/trunk/test/CodeGen/Hexagon/Atomics.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=273432&r1=273431&r2=273432&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Jun 22 11:07:10 2016
@@ -1715,6 +1715,9 @@ HexagonTargetLowering::HexagonTargetLowe
   setMinFunctionAlignment(2);
   setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
 
+  setMaxAtomicSizeInBitsSupported(64);
+  setMinCmpXchgSizeInBits(32);
+
   if (EnableHexSDNodeSched)
     setSchedulingPreference(Sched::VLIW);
   else
@@ -3121,3 +3124,10 @@ bool HexagonTargetLowering::shouldExpand
   // Do not expand loads and stores that don't exceed 64 bits.
   return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
 }
+
+bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
+      AtomicCmpXchgInst *AI) const {
+  const DataLayout &DL = AI->getModule()->getDataLayout();
+  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
+  return Size >= 4 && Size <= 8;
+}

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=273432&r1=273431&r2=273432&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Wed Jun 22 11:07:10 2016
@@ -256,6 +256,8 @@ bool isPositiveHalfWord(SDNode *N);
         Value *Addr, AtomicOrdering Ord) const override;
     AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
+    bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
+
     AtomicExpansionKind
     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
       return AtomicExpansionKind::LLSC;

Modified: llvm/trunk/test/CodeGen/Hexagon/Atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/Atomics.ll?rev=273432&r1=273431&r2=273432&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/Atomics.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/Atomics.ll Wed Jun 22 11:07:10 2016
@@ -69,3 +69,16 @@ entry:
 return:                                           ; preds = %entry
   ret void
 }
+
+
+define i64 @fred() nounwind {
+entry:
+  %s0 = cmpxchg i32* undef, i32 undef, i32 undef seq_cst seq_cst
+  %s1 = extractvalue { i32, i1 } %s0, 0
+  %t0 = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
+  %t1 = extractvalue { i64, i1 } %t0, 0
+  %u0 = zext i32 %s1 to i64
+  %u1 = add i64 %u0, %t1
+  ret i64 %u1
+}
+