[PATCH] D21560: Relax the clearance calculating for breaking partial register dependency.

[Michael Kuperstein via llvm-commits]

mkuper added a comment.

This mostly makes sense to me. 16 is as much of a magic number as 64, so if this is supported by performance numbers, it's fine.

The problem is that we're using the number of instructions between the write and the read as a proxy for the "the latency of the critical chain between the write and the read". And it's not a very good proxy, since it means how correct we are depends on how much ILP the loop (assuming this is a loop-carried dependency) has. So any number we have here will be just hand-waving.

Adding some Intel people in case they have more input.


http://reviews.llvm.org/D21560