[llvm] r273277 - [AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Silviu Baranga via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 21 08:53:55 PDT 2016
Author: sbaranga
Date: Tue Jun 21 10:53:54 2016
New Revision: 273277
URL: http://llvm.org/viewvc/llvm-project?rev=273277&view=rev
Log:
[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=273277&r1=273276&r2=273277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Tue Jun 21 10:53:54 2016
@@ -176,6 +176,24 @@ def ProcA57 : SubtargetFeature<"a57"
FeaturePredictableSelectIsExpensive
]>;
+def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
+ "Cortex-A72 ARM processors", [
+ FeatureCRC,
+ FeatureCrypto,
+ FeatureFPARMv8,
+ FeatureNEON,
+ FeaturePerfMon
+ ]>;
+
+def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
+ "Cortex-A73 ARM processors", [
+ FeatureCRC,
+ FeatureCrypto,
+ FeatureFPARMv8,
+ FeatureNEON,
+ FeaturePerfMon
+ ]>;
+
def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
"Cyclone", [
FeatureAlternateSExtLoadCVTF32Pattern,
@@ -236,8 +254,8 @@ def : ProcessorModel<"cortex-a35", Corte
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
// FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
-def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
-def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA57]>;
+def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
+def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=273277&r1=273276&r2=273277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Tue Jun 21 10:53:54 2016
@@ -74,6 +74,8 @@ void AArch64Subtarget::initializePropert
case Vulcan: break;
case CortexA35: break;
case CortexA53: break;
+ case CortexA72: break;
+ case CortexA73: break;
case Others: break;
}
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=273277&r1=273276&r2=273277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Tue Jun 21 10:53:54 2016
@@ -39,6 +39,8 @@ public:
CortexA35,
CortexA53,
CortexA57,
+ CortexA72,
+ CortexA73,
Cyclone,
ExynosM1,
Kryo,
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