[llvm] r273255 - [TargetSchedule] Use 'isOutOfOrder' as possible to avoid magic number. NFC.

Junmo Park via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 21 01:09:58 PDT 2016


Author: flyingforyou
Date: Tue Jun 21 03:09:58 2016
New Revision: 273255

URL: http://llvm.org/viewvc/llvm-project?rev=273255&view=rev
Log:
[TargetSchedule] Use 'isOutOfOrder' as possible to avoid magic number. NFC.

Summary:
Using isOutOfOrder makes the code more clear.

Reviewers: rengolin, atrick, hfinkel.

Differential Revision: http://reviews.llvm.org/D21548

Modified:
    llvm/trunk/lib/CodeGen/TargetSchedule.cpp

Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=273255&r1=273254&r2=273255&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Jun 21 03:09:58 2016
@@ -267,11 +267,10 @@ TargetSchedModel::computeInstrLatency(co
 unsigned TargetSchedModel::
 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
                      const MachineInstr *DepMI) const {
-  if (SchedModel.MicroOpBufferSize <= 1)
+  if (!SchedModel.isOutOfOrder())
     return 1;
 
-  // MicroOpBufferSize > 1 indicates an out-of-order processor that can dispatch
-  // WAW dependencies in the same cycle.
+  // Out-of-order processor can dispatch WAW dependencies in the same cycle.
 
   // Treat predication as a data dependency for out-of-order cpus. In-order
   // cpus do not need to treat predicated writes specially.




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