[PATCH] D21534: GlobalISel: first outline of legalization interface.

[Matt Arsenault via llvm-commits]

arsenm added a subscriber: arsenm.

================
Comment at: include/llvm/CodeGen/GlobalISel/MachineLegalizeInfo.h:25-28
@@ +24,6 @@
+namespace llvm {
+class Type;
+class VectorType;
+class MachineInstr;
+class LLVMContext;
+
----------------
Alphabetize

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Comment at: include/llvm/CodeGen/GlobalISel/MachineLegalizeInfo.h:33-40
@@ +32,10 @@
+public:
+  enum LegalizeAction : std::uint8_t {
+    Legal,
+    NarrowScalar,
+    WidenScalar,
+    FewerElements,
+    MoreElements,
+    Libcall,
+    Custom,
+  };
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These need descriptive comments. Can we also add an unsupported / error on option?

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Comment at: include/llvm/CodeGen/GlobalISel/MachineLegalizeInfo.h:45
@@ +44,3 @@
+
+  /// Compute any ancilliary tables needed to quickly decide how an operation
+  /// should be handled. This must be called after all "set*Action"methods but
----------------
Typo ancillary 

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Comment at: include/llvm/Target/GenericOpcodes.td:24
@@ +23,3 @@
+  let InOperandList = (ins unknown:$src);
+  let AsmString = "";
+  let hasSideEffects = 0;
----------------
Isn't this the default?

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Comment at: include/llvm/Target/GenericOpcodes.td:30
@@ +29,3 @@
+// G_EXTRACT for scalar types, but acts elementwise on vectors.
+def G_TRUNCATE : Instruction {
+  let OutOperandList = (outs unknown:$dst);
----------------
I think this should be trunc to match the IR instruction name

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Comment at: include/llvm/Target/GenericOpcodes.td:66
@@ +65,3 @@
+  let OutOperandList = (outs unknown:$dst, unknown:$carry_out);
+  let InOperandList = (ins unknown:$src1, unknown:$src2, unknown:$carry_in);
+  let AsmString = "";
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0 indexed src name? Should named operand tables somehow work with the generic opcodes?

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Comment at: include/llvm/Target/GenericOpcodes.td:75
@@ +74,3 @@
+// have been selected.
+def G_EXTRACT : Instruction {
+  let OutOperandList = (outs unknown:$dst);
----------------
EXTRACT_SUBREG?

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Comment at: include/llvm/Target/GenericOpcodes.td:97
@@ +96,3 @@
+// bit 0).
+def G_SEQUENCE : Instruction {
+  let OutOperandList = (outs unknown:$dst);
----------------
REG_SEQUENCE?


Repository:
  rL LLVM

http://reviews.llvm.org/D21534