[PATCH] D21482: Support/ELF: Add R_AMDGPU_GOTPCREL relocation

[Tom Stellard via llvm-commits]

tstellarAMD updated this revision to Diff 61154.
tstellarAMD added a comment.

clang-format the patch.


http://reviews.llvm.org/D21482

Files:
  docs/CodeGenerator.rst
  include/llvm/Support/ELFRelocs/AMDGPU.def
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -46,6 +46,13 @@
   if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
     return ELF::R_AMDGPU_ABS32_HI;
 
+  switch (Target.getAccessVariant()) {
+  default:
+    break;
+  case MCSymbolRefExpr::VK_GOTPCREL:
+    return ELF::R_AMDGPU_GOTPCREL;
+  }
+
   switch (Fixup.getKind()) {
   default: break;
   case FK_PCRel_4:
Index: include/llvm/Support/ELFRelocs/AMDGPU.def
===================================================================
--- include/llvm/Support/ELFRelocs/AMDGPU.def
+++ include/llvm/Support/ELFRelocs/AMDGPU.def
@@ -9,3 +9,4 @@
 ELF_RELOC(R_AMDGPU_REL32,         4)
 ELF_RELOC(R_AMDGPU_REL64,         5)
 ELF_RELOC(R_AMDGPU_ABS32,         6)
+ELF_RELOC(R_AMDGPU_GOTPCREL,      7)
Index: docs/CodeGenerator.rst
===================================================================
--- docs/CodeGenerator.rst
+++ docs/CodeGenerator.rst
@@ -2676,6 +2676,9 @@
 
 * **A** --- Represents the addend used to compute the value of the relocatable
   field
+* **G** --- Represents the offset into the global offset table at which the
+  relocation entry’s symbol will reside during execution.
+* **GOT** --- Represents the address of the global offset table.
 * **P** --- Represents the place (section offset or address) of the storage unit
   being relocated (computed using ``r_offset``)
 * **S** --- Represents the value of the symbol whose index resides in the
@@ -2694,4 +2697,5 @@
   ``R_AMDGPU_REL32``     4      ``word32``  S + A - P
   ``R_AMDGPU_REL64``     5      ``word64``  S + A - P
   ``R_AMDGPU_ABS32``     6      ``word32``  S + A
+  ``R_AMDGPU_GOTPCREL    7      ``word32``  G + GOT + A - P
   =====================  =====  ==========  ====================


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