[llvm] r272860 - AMDGPU: Disable scheduling in some slow tests

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Jun 15 19:56:47 2016
New Revision: 272860

URL: http://llvm.org/viewvc/llvm-project?rev=272860&view=rev
Log:
AMDGPU: Disable scheduling in some slow tests

Disabling the pre-RA scheduler on large-work-group-registers
causes it to be ~50% slower.

Modified:
    llvm/trunk/test/CodeGen/AMDGPU/large-work-group-registers.ll
    llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

Modified: llvm/trunk/test/CodeGen/AMDGPU/large-work-group-registers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/large-work-group-registers.ll?rev=272860&r1=272859&r2=272860&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/large-work-group-registers.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/large-work-group-registers.ll Wed Jun 15 19:56:47 2016
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga -post-RA-scheduler=0 < %s | FileCheck %s
 
 ; CHECK: NumVgprs: 64
 define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, <3 x i32> inreg, <3 x i32> inreg, <3 x i32>) #0 {

Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll?rev=272860&r1=272859&r2=272860&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll Wed Jun 15 19:56:47 2016
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s
-; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga < %s | FileCheck %s
-;
+; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
+; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
+ ;
 ; There is something about Tonga that causes this test to spend a lot of time
 ; in the default register allocator.