[llvm] r272836 - [Hexagon] Fix/simplify some conditional statements

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jun 15 16:05:04 2016
New Revision: 272836

URL: http://llvm.org/viewvc/llvm-project?rev=272836&view=rev
Log:
[Hexagon] Fix/simplify some conditional statements

Fix for PR28138.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=272836&r1=272835&r2=272836&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Jun 15 16:05:04 2016
@@ -1530,7 +1530,7 @@ bool HexagonInstrInfo::areMemAccessesTri
   unsigned SizeA = 0, SizeB = 0;
 
   if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
-      MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
+      MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
     return false;
 
   // Instructions that are pure loads, not loads and stores like memops are not
@@ -3673,8 +3673,8 @@ HexagonII::SubInstructionGroup HexagonIn
   case Hexagon::S4_storeirb_io:
     // memb(Rs+#u4) = #U1
     Src1Reg = MI->getOperand(0).getReg();
-    if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
-        isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
+    if (isIntRegForSubInst(Src1Reg) &&
+        MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) &&
         MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
       return HexagonII::HSIG_S2;
     break;