[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

[Chuang-Yu Cheng via llvm-commits]

cycheng added a comment.

In http://reviews.llvm.org/D20310#457783, @amehsan wrote:

> As we discussed, before you commit the change, please add -verify-machineinstrs to your regression tests. No need to upload the patch again. Thanks.


Done! Thanks!

Hi Hal,

Looks like we can eliminate my stack slot tracking by force using STXVD2X/LXVD2X when HasVSX is true. I have tested my full test-set, we only need to update 2 llc test cases.

By the way, Spec2006 config I used in testing:

1. -m64 -O3 -mcpu=power8
2. -m64 -O1 -mcpu=power8 -mno-vsx

CY


================
Comment at: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp:451
@@ +450,3 @@
+    // (Please synchronize with PPCAsmPrinter::printOperand)
+    if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg)) {
+      if (isVRRegister(Reg))
----------------
hfinkel wrote:
> Can you please use something like this instead:
> 
>   MI->getDesc().OpInfo[MO's index].RegClass == PPC::VFRCRegClassID
> 
> and then get rid of the UseVSXReg flag?
1. I tried it, but I got failed, the reason was: RegClass return Super Register Class name, i.e. VSRC in our case, so when I get VSRC, I won't be able to know it is VRRC or VSLRC. And we only want to translate VRRC, not VSLRC.

```
    const MCInstrDesc &MCID = MI->getDesc();

    if (MCID.TSFlags & PPCII::UseVSXReg) {
      int RCID = MCID.OpInfo[OpNo].RegClass;

      if (RCID == PPC::VRRCRegClassID)
        Reg = PPC::VSX32 + (Reg - PPC::V0);
      else if (RCID == PPC::VFRCRegClassID)
        Reg = PPC::VSX32 + (Reg - PPC::VF0);
    }
```

2. Probably not! Because the information is not enough. When the input register is VRRC, I won't know whether it is Altivec instruction, or VSX instruction, I need a flag for this. (so I need to tag the information in PPCInstrVSX.td)

So when UseVSXReg == true:
1. MI is a VSX
2. MI uses VSX registers

when UseVSXReg == false:
1. MI can be a VSX or Altivec, but they both use Altivec registers



http://reviews.llvm.org/D20310