[llvm] r272543 - This patch fixes handling long double type when it is
Strahinja Petrovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 13 03:29:29 PDT 2016
Author: spetrovic
Date: Mon Jun 13 05:29:29 2016
New Revision: 272543
URL: http://llvm.org/viewvc/llvm-project?rev=272543&view=rev
Log:
This patch fixes handling long double type when it is
constant in soft float mode on PowerPC 32 architecture.
Added:
llvm/trunk/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=272543&r1=272542&r2=272543&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon Jun 13 05:29:29 2016
@@ -149,9 +149,26 @@ SDValue DAGTypeLegalizer::SoftenFloatRes
if (isLegalInHWReg(N->getValueType(ResNo)))
return SDValue(N, ResNo);
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
- return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
- TLI.getTypeToTransformTo(*DAG.getContext(),
- CN->getValueType(0)));
+ // In ppcf128, the high 64 bits are always first in memory regardless
+ // of Endianness. LLVM's APFloat representation is not Endian sensitive,
+ // and so always converts into a 128-bit APInt in a non-Endian-sensitive
+ // way. However, APInt's are serialized in an Endian-sensitive fashion,
+ // so on big-Endian targets, the two doubles are output in the wrong
+ // order. Fix this by manually flipping the order of the high 64 bits
+ // and the low 64 bits here.
+ if (DAG.getDataLayout().isBigEndian() &&
+ CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
+ uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
+ CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
+ APInt Val(128, words);
+ return DAG.getConstant(Val, SDLoc(CN),
+ TLI.getTypeToTransformTo(*DAG.getContext(),
+ CN->getValueType(0)));
+ } else {
+ return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
+ TLI.getTypeToTransformTo(*DAG.getContext(),
+ CN->getValueType(0)));
+ }
}
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
Added: llvm/trunk/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll?rev=272543&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll Mon Jun 13 05:29:29 2016
@@ -0,0 +1,24 @@
+; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
+
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-buildroot-linux-gnu"
+
+ at .str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
+
+define i32 @main() #0 {
+entry:
+ %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), ppc_fp128 0xM3FF00000000000000000000000000000)
+ ret i32 0
+}
+
+; First available register for long double argument is r4, so put
+; Hi part in r4/r5, Lo part in r6/r7 (do not switch Hi/Lo parts)
+; CHECK: lis 4, 16368
+; CHECK-NOT: lis 6, 16368
+; CHECK: li 5, 0
+; CHECK: li 7, 0
+
+declare i32 @printf(i8* nocapture readonly, ...)
+
+attributes #0 = { "use-soft-float"="true" }
+
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