[PATCH] D19719: [mips][atomics] Fix atomic instruction descriptions and uses.

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM with PTRPredicates in the listconcat and a couple nits.


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Comment at: lib/Target/Mips/Mips.td:37-42
@@ -34,8 +36,8 @@
   list<Predicate> AdditionalPredicates = [];
   list<Predicate> Predicates = !listconcat(EncodingPredicates,
                                            GPRPredicates,
                                            FGRPredicates,
                                            InsnPredicates,
                                            HardFloatPredicate,
                                            AdditionalPredicates);
 }
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You need to add PTRPredicates to this listconcat() for the predicates in the sublist to take effect.

Once you've fixed this, we shouldn't need the separate DecoderNamespace anymore but tablegen might not be able to figure this out (it couldn't for the GPR_64 case). If we can eliminate the separate namespace then please do so, but I'm ok with it if we can't.

================
Comment at: lib/Target/Mips/Mips32r6InstrInfo.td:765
@@ -765,1 +764,3 @@
+  def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
+  def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
 }
----------------
Could you move this one back down to the SDBBP instruction? The instructions in this file are in alphabetical order

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:182
@@ -181,1 +181,3 @@
                       AssemblerPredicate<"!FeatureGP64Bit">;
+def IsPTR64bit    :    Predicate<"Subtarget->isABI_N64()">,
+                      AssemblerPredicate<"FeaturePTR64Bit">;
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This indentation hasn't been corrected


http://reviews.llvm.org/D19719