[polly] r272515 - [NFC] Outline the application of register tiling.

[Roman Gareev via llvm-commits]

Author: romangareev
Date: Sun Jun 12 12:20:05 2016
New Revision: 272515

URL: http://llvm.org/viewvc/llvm-project?rev=272515&view=rev
Log:
[NFC] Outline the application of register tiling.

Modified:
    polly/trunk/include/polly/ScheduleOptimizer.h
    polly/trunk/lib/Transform/ScheduleOptimizer.cpp

Modified: polly/trunk/include/polly/ScheduleOptimizer.h
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScheduleOptimizer.h?rev=272515&r1=272514&r2=272515&view=diff
==============================================================================
--- polly/trunk/include/polly/ScheduleOptimizer.h (original)
+++ polly/trunk/include/polly/ScheduleOptimizer.h Sun Jun 12 12:20:05 2016
@@ -90,6 +90,16 @@ private:
   tileNode(__isl_take isl_schedule_node *Node, const char *Identifier,
            llvm::ArrayRef<int> TileSizes, int DefaultTileSize);
 
+  /// @brief Tile a schedule node and unroll point loops.
+  ///
+  /// @param Node            The node to register tile.
+  /// @param TileSizes       A vector of tile sizes that should be used for
+  ///                        tiling.
+  /// @param DefaultTileSize A default tile size that is used for dimensions
+  static __isl_give isl_schedule_node *
+  applyRegisterTiling(__isl_take isl_schedule_node *Node,
+                      llvm::ArrayRef<int> TileSizes, int DefaultTileSize);
+
   /// @brief Check if this node is a band node we want to tile.
   ///
   /// We look for innermost band nodes where individual dimensions are marked as

Modified: polly/trunk/lib/Transform/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Transform/ScheduleOptimizer.cpp?rev=272515&r1=272514&r2=272515&view=diff
==============================================================================
--- polly/trunk/lib/Transform/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/Transform/ScheduleOptimizer.cpp Sun Jun 12 12:20:05 2016
@@ -335,6 +335,17 @@ ScheduleTreeOptimizer::tileNode(__isl_ta
   return Node;
 }
 
+__isl_give isl_schedule_node *
+ScheduleTreeOptimizer::applyRegisterTiling(__isl_take isl_schedule_node *Node,
+                                           llvm::ArrayRef<int> TileSizes,
+                                           int DefaultTileSize) {
+  auto *Ctx = isl_schedule_node_get_ctx(Node);
+  Node = tileNode(Node, "Register tiling", TileSizes, DefaultTileSize);
+  Node = isl_schedule_node_band_set_ast_build_options(
+      Node, isl_union_set_read_from_str(Ctx, "{unroll[x]}"));
+  return Node;
+}
+
 bool ScheduleTreeOptimizer::isTileableBandNode(
     __isl_keep isl_schedule_node *Node) {
   if (isl_schedule_node_get_type(Node) != isl_schedule_node_band)
@@ -374,13 +385,9 @@ ScheduleTreeOptimizer::standardBandOpts(
     Node = tileNode(Node, "2nd level tiling", SecondLevelTileSizes,
                     SecondLevelDefaultTileSize);
 
-  if (RegisterTiling) {
-    auto *Ctx = isl_schedule_node_get_ctx(Node);
-    Node = tileNode(Node, "Register tiling", RegisterTileSizes,
-                    RegisterDefaultTileSize);
-    Node = isl_schedule_node_band_set_ast_build_options(
-        Node, isl_union_set_read_from_str(Ctx, "{unroll[x]}"));
-  }
+  if (RegisterTiling)
+    Node =
+        applyRegisterTiling(Node, RegisterTileSizes, RegisterDefaultTileSize);
 
   if (PollyVectorizerChoice == VECTORIZER_NONE)
     return Node;