[PATCH] D21235: [x86, SSE] change patterns for CMPP to float types to allow matching with SSE1 (PR28044)

[Sanjay Patel via llvm-commits]

spatel created this revision.
spatel added reviewers: ab, RKSimon, craig.topper.
spatel added a subscriber: llvm-commits.
Herald added a subscriber: mcrosier.

This patch is intended to solve:
https://llvm.org/bugs/show_bug.cgi?id=28044

By changing the definition of X86ISD::CMPP to use float types, we allow it to be created and pass legalization for an SSE1-only target where v4i32 is not legal.

The motivational trail for this change includes:
https://llvm.org/bugs/show_bug.cgi?id=28001

and eventually makes this trigger:
http://reviews.llvm.org/D21190

Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86 intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86 intrinsics, a big pile of generic optimizations can trigger.

http://reviews.llvm.org/D21235

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/sse1.ll

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